Commits

Commits on Apr 20, 2025

test_rs: Use proc macro attribute to define trap handlers
tux3
committed
c04dc9b
Rust test for switching between M and U modes
tux3
committed
63e2be5
exec_system: Fix missing checks for WFI in U mode
tux3
committed
abc705b
Makefile: Remove # commands for empty targets
tux3
committed
9567e6b
Default test makefile target now also runs test_rs
tux3
committed
8797d0b
Fix test_rs start files to use a naked start function
tux3
committed
edb5edb
test_rs: Save waveforms under different filename per test
tux3
committed
5322161
axi4lite_tohost: Buffer and output line-by-line
tux3
committed
875d49f
Use test_soc in test_rs and add debug_println function
tux3
committed
2ea90b9
Add test_soc optimized for running C/Rust tests in simulator
tux3
committed
3efb074
Basic AXI4-Lite tohost device, implementing only text output
tux3
committed
c84a064
Fix exec_div_log2 unique if QuestaSim warning
tux3
committed
04d6972
Update edalize build to use uv and pyproject
tux3
committed
675cc23
High-level Rust tests using fail/success GPIO signals
tux3
committed
d04a4f0

Commits on Apr 15, 2025

Rename riscv-tests -> riscv_tests
tux3
committed
1812c7f
Refactor xRET CSR update to be in csrs.sv, not exec_system.sv
tux3
committed
c7493a4
Set MPP to USER on xRET (USER is the smallest supported)
tux3
committed
98317ec
Allow MPP to hold values lower than MACHINE
tux3
committed
e84e611
Update current privilege mode (to M) on trap
tux3
committed
f639a7f
Check CSR access against current privilege level
tux3
committed
1e2cf98
Fix csr is_read_instr typo, condition was always true
tux3
committed
d51e618
Set mstatus.TW=1 and raise exception on WFI instruction in U mode
tux3
committed
8cd87fc

Commits on Apr 13, 2025

Update Rust code for new nightly changes, enable Zba target-feature
tux3
committed
93c46a9
Implement Zba, completing our support for the Bitmanip B extension
tux3
committed
4bc565c
Makefile to run the RISC-V Compatibility Framework riscv-arch-tests
tux3
committed
bc53760
EBREAK should set mtval to the instruction virtual address
tux3
committed
542729c
Fix AMO .W instructions to properly ignore high bits
tux3
committed
264a6de
Fix rs1_mul_sign/rs2_mul_sign ignoring exec bypass
tux3
committed
f688e1c
Decompress: Fix handling of C.ADD HINT (rd = 0)
tux3
committed
c4b153e
SRLW/SRLIW: Fix edge-case of sign-extending zero-shifted signed input
tux3
committed
0a44424
exec_div: Turn unique if into unique0, since it fallbacks into 'x
tux3
committed
b79052f
Plugin to run riscv-arch-tests through a QuestaSim testbench
tux3
committed
f019883
basic_cache: Fix typo that made cache 2x smaller than intended
tux3
committed
3a74dc8
Take memory init file for axi4lite_sram in testbenches
tux3
committed
bc9eedb
basic_soc: Parametrize axi4lite SRAM size
tux3
committed
102a39f