Information and documentation for Tang Nano 20K on Sipeed WIKI
Be aware of some caveats when using GPIO pins. See pinout.
Discussion group on Telegram
TEAM members, feel free to fork or create any repository that has a working core or is related to Tang nano 20k.
Forked repositories with no local commits that are behind upstream repository need to be synced (Sync fork button). No team members should visit the upstream repository page for latest commits.
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Nano 20K and Primer 20K boards
Flappy Bird core for MiSTer, MiST, DeMiSTify, Pocket, Xilinx, GoWin, ...
NESTang SDRAM controller usage example
KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, linux soc included, .
A compact USB HID host FPGA core supporting keyboards, mice and gamepads.
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