Former aerospace technician turned embedded systems researcher.
I design high-integrity platforms rooted in PLC control, automation security, and reproducible education tools.

Current focus: Time synchronization, latency, and jitter in OT/ICS networks
Driven by mission clarity, process fidelity, and system resilience.

University of Idaho Coeur d'Alene | Embedded Systems Research
Focus Areas: OT/ICS Security • Industrial Automation • Educational Infrastructure

Current Research: Time synchronization, latency, and jitter measurement in OT/ICS networks
Next Phase: Graduate research in industrial control system security architectures

• Raspberry Pi–based measurement platform for latency & jitter in OT/ICS environments
• Objective: Quantify timing stability of baseline LAN vs. Zero Trust (ZT) overlays
• Technologies: Raspberry Pi 4B (8GB), Chrony, iperf, custom Python parsing
• Impact: Reproducible research data on ZT adoption risks in ICS/OT networks
• Context: University of Idaho Cybersecurity research with faculty advisors → Zero Trust Latency Testbed

Research-grade PLC training system built on Arduino Opta

• Technologies: Ladder Logic, IEC 61131-3, Modbus TCP integration
• Integration: SCADA-ready via Ignition HMI
• Impact: Curriculum modules, instructor guides, and DEVLOG tracking
• Context: Part of University of Idaho embedded systems research spine
  → PLC Student Demo Platform

Python interface between Linux and Arduino Opta PLCs

• Purpose: Serial USB communication with logic filtering
• Features: Automation safety protocols, modular lab system integration
• Architecture: Clean Python package structure with comprehensive error handling
• Applications: Research prototyping, educational demonstrations, OT security testing → PLC-Bridge Repository

Hardened C utility demonstrating defensive parsing and fuzz-verified robustness

• Purpose: Secure coding exercise emphasizing correctness over features
• Security Controls: Strict input grammar, bounded strings, integer safety
• Verification: AFL fuzzed (~14.5 hours, ~143M executions, zero crashes/hangs)
• Context: Developed for a Secure Coding course at the University of Idaho
• Status: Complete and intentionally archived after meeting security objectives → Secure C Calculator

Current: University of Idaho – Coeur d'Alene
Degree: B.S. Cybersecurity (ICS/OT Security Track)
Role: Undergraduate Research Assistant – Time synchronization, latency, and jitter measurement in OT/ICS networks

Completed: North Idaho College
Degree: A.S. Computer Science
Highlights: Dean's List, Team Project Leadership

Research Portfolio:
Building comprehensive research documentation in embedded systems and ICS security for graduate study preparation and laboratory deployment initiatives.

• Research: Time synchronization, latency, and jitter measurement in OT/ICS networks
• Security: Understanding timing-related failure modes and attack surfaces in industrial systems
• Infrastructure: Building reproducible measurement testbeds (Raspberry Pi, PLC-adjacent systems)
• Documentation: Producing research-grade notes, datasets, and methodology artifacts