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Lightweight and highly scalable Python register abstraction layer

Python 5 1 Updated Jun 3, 2026

A type-safe, formally verifiable HDL compiler in Lean 4. Inspired by Clash, built for high-assurance hardware synthesis.

Lean 81 12 Updated Jun 14, 2026

An analog simulator bridge for cocotb — open-source mixed-signal co-simulation

Python 9 2 Updated Mar 19, 2026

Provides a stub implementation of (System)Verilog VPI functions for SystemC

C 4 2 Updated Feb 17, 2026

A Pythonic implementation of SystemVerilog-style Interface, Modport, and Clocking Block for cocotb. Bridge the gap between hardware verification concepts and Python with race-free, timing-accurate …

Python 5 1 Updated Mar 5, 2026
C++ 114 59 Updated Jun 10, 2026
Python 14 5 Updated May 19, 2026

NVIDIA Holoscan Sensor Bridge - Bring Your Own Sensor (BYOS) over Ethernet

C++ 46 25 Updated Jun 12, 2026

Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

SystemVerilog 406 108 Updated Jun 13, 2026

This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Python-like test style while potentially improving simulation p…

C++ 28 1 Updated Feb 16, 2026

Coverview

Vue 32 6 Updated Jun 3, 2026

LLM-based transistor sizing for AMS circuits

Jupyter Notebook 29 11 Updated Apr 23, 2026

55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.

Verilog 210 23 Updated May 22, 2026

Staging area for new features of cocotb

C++ 5 2 Updated Jun 13, 2026

Generate Python Register Access Layer (RAL) from SystemRDL

Python 13 4 Updated May 24, 2026
C++ 98 9 Updated May 20, 2026
Python 1 Updated Oct 8, 2025

Apheleia Verification Library - AMBA Advanced Peripheral Bus verification component

Python 6 2 Updated Mar 27, 2026

Seamless integration between Python and SystemVerilog

6 Updated Apr 11, 2025

A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …

SystemVerilog 87 22 Updated May 8, 2026

This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from Cologne Chip

Verilog 20 1 Updated Jul 28, 2025

The HW-CBMC and EBMC Model Checkers for Verilog

C++ 109 24 Updated Jun 14, 2026

Cocotb v2 Code Migration Helper

Python 8 Updated Aug 19, 2025

SpiceBind – spice inside HDL simulator

C++ 58 6 Updated Jun 30, 2025

Open-source repository for a standard-cell library characterizer using complete open-source tools

Python 62 17 Updated Jun 8, 2026

An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。

Verilog 156 35 Updated Sep 15, 2023

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器,可实现高压缩率的无损/近无损图像压缩。

Verilog 323 62 Updated Sep 18, 2024

Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM

VHDL 45 3 Updated Jul 11, 2025

Open-source RTL logic simulator with CUDA acceleration

Rust 279 26 Updated Sep 30, 2025
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