This repository contains the design files of RISC-V Pipeline Core

A high-performance inference engine for AI models

Single Cycle CPU using the RV32I Base Instruction set

Development repository for the Triton language and compiler

Vivado 2023.2 project built around the CVA6 RISC-V CPU and a software stack including u-boot and embedded linux.

A DSL for Systolic Arrays

Working draft of the proposed RISC-V V vector extension

VIP for AXI Protocol

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

UART implementation using verilog

BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

Structured UVM Course

Source files for SiFive's Freedom platforms

Открытое RISC-V процессорное ядро MIRISCV для образовательных целей

APB master and slave developed in RTL.

Verilog digital signal processing components

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

AMBA AXI VIP

Single Cycle Processor written in SystemVerilog for executing machine code of RISC-V ISA

mor1kx - an OpenRISC 1000 processor IP core

Tile based architecture designed for computing efficiency, scalability and generality

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

A Verilog based 5-stage fully functional pipelined RISC-V Processor code.

SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator based on a GeMM systolic array engine.

My implementation of the RISC-V Single Cycle Processor, based on the Textbook - Digital Design and Computer Architecture: RISC-V Edition by Sarah Harris and David Harris

Opensource DDR3 Controller

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions