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This project contains (in the v2_xdma directory) the significantly modified driver for Xilinx XDMA IP core, together with the HDL code. It allows high-speed cyclic transfer to the huge memory buffers directly mapped to the application memory.

The v1_dmover directory contains the uncompleted driver for the PCIe DMA based on the DataMover and AXI MMapped to Memory block.

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  • C 62.2%
  • Verilog 16.0%
  • Tcl 11.9%
  • VHDL 4.2%
  • SystemVerilog 4.0%
  • C++ 0.8%
  • Other 0.9%