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@OpenXiangShan
XiangShan OpenXiangShan
Open-source high-performance RISC-V processor
@bonfireprocessor
Bonfire Processor bonfireprocessor
@qubeck78
Michał Kubecki qubeck78

Pszczyna, Poland

@stnolting
stnolting
Roads? Where we're going we don't need roads. - "Doc" Emmett L. Brown

@fraunhofer-ims 🇪🇺 European Union

@f32c
f32c
RISC-V / MIPS ISA retargetable CPU core
@gojimmypi
gojimmypi gojimmypi
Gizmos! Embedded Devices @wolfSSL; B.S. Electronic Engineering from @calpoly; Senior Software Engineer @ Day Job: SQL C# dotnet.

wolfSSL Inc. California

@tomverbeure
Tom Verbeure tomverbeure
24/7 electronics (and some biking)

Sunnyvale, CA

@YosysHQ
Yosys Headquarters YosysHQ
Yosys Open SYnthesis Suite
@riscv-non-isa
RISC-V Non-ISA Specifications riscv-non-isa
The Open-Standard Instruction Set Architecture

Switzerland

@zeldin
Marcus Comstedt zeldin

Linköping

@pymtl
PyMTL pymtl
A Python-Based Ecosystem for Hardware Modeling, Generation, Simulation, and Verification
@MattPD
Matt MattPD
@cyrus-and
Andrea Cardaci cyrus-and
uid=0(root) gid=0(root) groups=0(root)

PWD=/italy/tuscany/pisa

@cs01
Chad Smith cs01
Creator of gdbgui, pipx, and TermPair. Developer infrastructure at Meta (Reality Labs).

Bay Area, CA

@vuvova
Sergei Golubchik vuvova
@angr
angr
Next-generation binary analysis framework!
@hugsy
crazy hugsy hugsy
Exploit Dev & OffSec Tool Dev

@blahcat Ring0