Low-level Apple Silicon memory benchmark for measuring cache latency and memory behavior on macOS (ARM64).

MIPS Cache-Memory-Page_Table Simulator

Simulating TLB and its interfacing with Page Table (Virtual memory concepts)

TUM Grundlagenpraktikum: Rechnerarchitektur S24 - Translation Lookaside Buffer - Grade 1.0

C++/Qt based component demonstrating how to interface and place an order with the Sterling Trading Platform. The Sterling Trading platform https://www.sterlingtradingtech.com/ does not support a C++ interface . I managed to generate a tlb from the distributed dll using OleView and interface to the library using COM.

C++ Virtual Memory Simulator with a Qt GUI for visualizing address translation, page faults, TLB operations, and page replacement strategies.