Autofill NetID when logging into Blackboard & syncs across signed-in Chrome browsers

Notifying students when their course of interest has availability.

Different concepts of SV, UVM ,Verilog and C noted down in the form of a blog.

Universal Virtual Machine for Node and Browser

A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.

Videojuego Proyecto Sistemas Web 2025

A gateway for amazing Web1337 by KLYNTAR

"Advanced Peripheral Bus (APB) Verification IP with UVM - Complete testbench with 13 comprehensive tests, GUI simulation, and coverage analysis"

links a materias de UVM