Generates multi channels sounds from primitives
Collection of lab exercises (prácticas) and code from various courses in the Industrial Engineer: Electronics-ICT program at the University of Antwerp. Organized by subject with VHDL and C++ as examples.
A 4-bit ripple-carry adder and a 4-bit register using Verilog HDL on a Basys-3 FPGA.
🏛️ [RUSHED🏃♀️] A study on VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language for Academics.
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
Kode i VHDL for utviklingskort DE-10, med FPGA Altera MAX 10M50DAF484C7G.
FPGA Hardware Simulation Framework
Getting started with VHDL: Very High Speed Integrated Circuit Hardware Description Language.
This repository contains the VHDL implementation of a ROM-less Direct Digital Frequency Synthesizer (DDFS) designed for high-speed calculation of the arctan function. This project was developed as a final assignment to fulfill the requirements for a bachelor's degree in my Electrical Engineering.
A simple and efficient VHDL implementation of an 8-bit PWM generator. It is designed to be clock-synchronous and features an asynchronous reset. Based on an 8-bit duty cycle input, the module generates a digital output signal with a modulated pulse width.
Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.
Logic & Digital Designs — VHDL — (Course: Logic Design / Digital Circuits, Semester X): small combinational and sequential VHDL designs (adders, encoders, counters, FSMs) with testbenches and waveforms, plus report.
Ejemplos de codigo con implementación en hardware para la tarjeta Cyclone IV lenguaje VHDL
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