Collection of FPGA modules for video capture and processing.

Workflow for executing CNN Networks on Zynq Ultrascale+ with Vitis AI toolchain. Detailed analysis, configuration and execution of Convolutional Neural Networks on ZCU102 using Vitis AI, evaluating performance on the board compared to Cloud infrastructure (eg. Kaggle). Developed for educational exam purposes.

SHA-256 (Secure Hash Algorithm 256-bit) hardware is implemented in Verilog and C and verifcated in SystemVerilog.

Xilinx Vitis repository containing video streaming and machine learning reference designs.

This repository contains the source code for implementing data exchange through the SFP+ Cages of the Xilinx's Multi-processor System-on-Chip (MPSoC)

AES-128 (Advanced Encryption Standard 128-bit) module written in Verilog for FPGA/ASIC use.

This directory contains the source code for implementing Random Linear Network Coding (RLNC) into Multi-Processor System-on-Chips (MPSoC). By exploiting data vectorization, we obtained latency and throughputs gains during the matrix multiplication operations.

Generate and install boot apps for the Zynq MPSoC device

✅ The testing program validates the BlueDBM flashboard for the ZCU102 motherboard.

ZCU102 two IMX274 camera design.

Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional Neural Networks on ZCU102 using VITIS AI, evaluating performance on the board compared to Cloud infrastructure. Developed for educational exam purposes.

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

A portable interface for energy monitoring utilities