#

bfm

Here are 4 public repositories matching this topic...

chili-chips-ba / openPCIE

Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource on the Host side too. Our project roots for the Root Port in 4 ways: |1|openRTL |2|openBFM with unique SIM setup, way faster than vendor's |3|openSW stack |4|one-of-a-kind open backplane.

fpga serdes driver pcb rtl backplane systemverilog rp pcie bfm

Updated Feb 4, 2026
Verilog

AXI_WB_TB

dg2300 / AXI_WB_TB

Basic UVM Testbench to verify AXI stream spec design. Added a wishbone BFM to mimic Wishbone design.

system-verilog bfm design-verification uvm-verification

Updated Dec 5, 2023
Verilog

vaseegoo / AXI3_VIP

Xillinx AXI Verification IP VLNV:axi_vip1.1@Vivado 2017.4

bfm axi3

Updated Aug 3, 2018
Verilog

vaseegoo / axi_vip

Xillinx AXI Verification IP :axi_vip1.1@Vivado 2017.4

vip bfm xillinx axi3

Updated Aug 3, 2018
Verilog

Improve this page

Add a description, image, and links to the bfm topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the bfm topic, visit your repo's landing page and select "manage topics."