HLS based Cordic Accelerator

Algorithms for calculating sine and cos with an input in degree. For now it only works for quadrant I. (This code is just for demonstration, not for implementation)

Just CORDIC, nothing much

Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London

High-performance CORDIC hardware accelerator on Zynq-7000 SoC with 16-stage pipeline and 0.05% error margin.基于Zynq-7000 SoC的高性能CORDIC硬件加速器，具有16级流水线和0.05%误差容限。

FPGA RTL design projects implemented in Verilog/SystemVerilog, including FSM architectures, CORDIC-based DSP modules, LFSR pseudo-random generators, fixed-point arithmetic units, and custom FIFO designs with verification testbenches.

The data captured from the Petalinux Environment over the Uart interface will be transmitted to the CORDIC IP and the results will be transmitted to the PC over the Uart.

IEEE-754 compliant float-integer conversion modules

Calculating sine and cosine using CORDIC algorithm in MIPS assembly. Project for Computer Architecture (ARKO) laboratories at Warsaw University of Technology.

Summary of projects I did in VLSI desing.

Cordic system implemented in VHDL FPGA (Spartan3E)

CORDIC FPGA implemtation on 7 segment display

A project in which Xilinx's CORDIC (COordinate Rotation DIgital Computer) IP is used as the hardware accelerator and the processor transfers the computational load to the hardware accelerator.

SystemVerilog CORDIC block that converts from an input phase (sawtooth wave) to a sine wave

STM32 cordic benchmark

Chisel implementation of a CORDIC design

A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance

A Naive CORDIC implementation

sin, cos, sinh, cosh, e^x and sqrt in ARM using CORDIC

Floating Point CORDIC Based Power Operation