🌱 Evolve your applications with the Evolution API, offering seamless integration and powerful features for enhanced development and user experience.

🔍 Conduct an in-depth review of Week 3 tasks for the VSD RV SoC Tapeout Program, showcasing key findings and insights.

A library for inspecting combinational digital circuits from Verilog netlists, focusing on exploring energy limits based on Landauer's principle.

Basic electrical simulation software with easy UI

Digital logic design tool and simulator

华中科技大学计算机个人资料合集:课设/实验报告等。tag:数电实验交通灯，C++实验华为，C语言实验，数据结构实验，洛谷算法实验，SAT数独求解器，电路理论，Java，计算机系统基础实验(CSAPP)，组原实验，计网，软件工程，操作系统、函数式编程，头歌

Hey, This is a contactless distance sensor, but not the usual Arduino kit build. I’m making it as a proper mixed-signal design using analog and digital parts, tuned for the best possible accuracy in the 10 to 50 cm range, with a practical form factor, ultra low average power use (below 2 mW) and keeping the cost as low as possible

Computer architecture for teaching and research in computer systems, with IDE, editor, assembler, linker, emulator, programming examples, digital circuit

Digital Up/Down counter using CD4029 and 74LS47 ICs with a single 7-segment display. Includes manual clock, reset, and direction control.

This repository contains the report of the Week 3 task for VSD RV SoC Tapeout Program

Clarify anything I'm interested in TypeScript until It can't. (Because TypeScript is good and fit to me for mapping out the domain).

SystemVerilog implementations of a 101 pattern detector using both structural and behavioral modeling styles. Includes separate testbenches for each implementation. Designed for detecting overlapping 101 patterns in a serial bitstream, useful for learning FSM design and simulation in digital systems.

Simulación en Logisim de un autómata finito que recorre nodos de “Bitópolis” a partir de un código de 4 bits, mostrando paso a paso el trayecto en un display de 7 segmentos hasta el nodo F.

This example implements a digital 8-bit sequential divider simulation on SimulIDE

This repo contains Digital Systems Design course assignments

My Undergraduate Experiment Code and Reports of Digital Circuit and Computer Organization Course

VHDL-based digital logic project from Politecnico di Milano, featuring a convolutional encoder for telecommunications. Implements a finite state machine (FSM) to process sequences from memory, doubling the number of output words.

Fritzing parts for most common DIP ICs including 74LS Series and more, which is used in Digital Electronics or Logic Circuit and Design.

HITSZ 2024 数字电子技术实验 FPGA Verilog 代码仓库