The purpose of this lab is to design a 4-bit counter using JK flip flops
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Updated
Mar 8, 2019
The purpose of this lab is to design a 4-bit counter using JK flip flops
INE5406 - Digital Systems
Coffee vending machine implementation designed for FPGAs (DE2-115 kit)
Repositório com os projetos elaborados durante a disciplina de Sistemas Digitais I (PCS3115)
Course project for COE528 implementing a bookstore application, applying object-oriented design, UML modeling, class hierarchies, and system abstraction to simulate core bookstore operations.
some mini-projects, developed in my digital system's class, based on: combinational/sequential logic design, hardware description languages (VHDL), datapath components, register-transfer level (RTL) design and introduction to programmable processors, with a physical implementation in SSI IC's, ASIC's, FPGA's, PLD's.
Neander++ (Neander extended) implementation and testing in VHDL for Digital Systems' 2nd assignment.
We aim to design a 3-bit two’s complement add/sub logic circuit.
Material académico y práctico de la UDA Circuitos Lógicos (MIE.SD01.09) – Maestría en Ingeniería Eléctrica.
Digital Pong Game Circuit for Digital Systems Lab - Electrical & Computer Engineering, NTUA 2025
Design a digital circuit that encodes and decodes strings with CRC-8 algorithm with an optimal delay and number of components
👾 My studies with Verilog and notions of digital systems.
digital systems(circuit based) simulation.
Design a system to detect a sequence of inputs.
This repository contains my assignments and projects for the Digital Systems course. The course covers the fundamental concepts of digital systems, including Boolean algebra, logic gates, combinational and sequential circuits, memory, and programmable logic devices. I have included VHDL code and simulation results for some of the projects.
Program the FPGA with mastermind game
Pacman implemented on DE1-SoC in Verilog
O objetivo do deste projeto foi modelar, programar e testar uma Unidade Lógica e Aritmética, de quatro operações, usando os conhecimentos adquiridos em Circuitos Lógicos e aplicados nas aulas práticas no laboratório de Sistemas Digitais.
A high-performance VHDL coprocessor for 3×3 matrix multiplication with FSM control unit and optimized processing pipeline
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