Persist and reuse KV Cache to speedup your LLM.

DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

Block-sparse for v5e-1 eliminates the O(N²) HBM attention matrix via online fused softmax, crossing the 240.2 FLOPs/byte ridge point at N≥1024

Thermal-aware batch controller for vLLM/TensorRT-LLM. Prevents HBM thermal throttling from killing p99 latency on H100/H200. Monitors nvidia-smi, auto-cuts batch size at 85°C, migrates cold KV to DRAM. Prometheus + Grafana included. 4.2s -> 2.1s p99 at 128K context.

A.F.O artifact for bridge-sensitive bottleneck attribution and control in hierarchical LLM memory paths (gem5-based reproducibility bundle).

🔲 Chip substrate — 28-verb semiconductor stack (architecture / design / EDA / process / packaging / NPU / PIM / 3D / photonic / RTL-gen / yield / consciousness-chip).

Reference simulator + benchmark harness for HBM residency control and fragmentation metrics.