High Speed Pipelined FPGA Architecture for Linear and Adaptive Median Image Filtering
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Updated
Apr 28, 2020 - VHDL
High Speed Pipelined FPGA Architecture for Linear and Adaptive Median Image Filtering
A VHDL description of a digital image filtering system on FPGAs. Part of COL215 course project.
An Image filter that takes in an image and applies the smoothening or sharpening filter on it depending on the user's choice.
Master thesis - image filtering with FPGA
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