My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA
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Jun 26, 2018 - Verilog
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network-on-chip
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A complete 1×3 NoC router implemented from RTL to GDSII using the Sky130A PDK. Includes full functional verification, synthesis (Yosys), and physical design using OpenLane/OpenROAD, culminating in a signoff-clean GDS layout.
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Dec 11, 2025 - Verilog
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