All Digital Phase-Locked Loop (ADPLL)
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Updated
Jan 16, 2024 - Verilog
All Digital Phase-Locked Loop (ADPLL)
Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
利用 GPS 与传感器,在移动设备上模拟飞机驾驶舱的 PFD。 / Simulate the cockpit PFD (Primary Flight Display) on mobile devices, by using GPS and sensors.
Popularity of names from the Alaska Permanent Fund Dividend (PFD).
A PFD (Process Flow Diagram) rendering toolkit and web modeler.
Python face detection using OpenCV with Cascade.
Design of Phase-Locked-Loop using 45nm technology on Cadence Virtuoso tool
This Project i made for my ÜK last autumn. Its ML and data analysis combined in a bit Documentation
AI and ML Models for Secure Digital Transactions at Blossom Bank
Tools related to Process Flow Diagram (PFD) such as static analyzers and schedulers
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