Unlike traditional PUF approaches that rely on static fingerprints, this system leverages **challenge-driven dynamic behavior (TrapOrbit)** to model and verify device identity.

verITA - Project Official Repository Hackathon Innovation Challenge

PoC Implementation of the Group Key PHEMAP protocol

Embedded Neural Firmware (ENF) - a sealed, offline 'Neural BIOS' for batteryless devices.

This repository contains source code and PCB designs for a switch matrix to measure carbon nanotube field-effect transistors.

Developed a linear model for a XOR-PUF system. Here the XOR-PUF consists of three PUFs, each with eight multiplexers, and takes an 8-bit challenge as input. The goal is to create a new feature vector from the challenge and use a linear model using gradient descent to predict the PUF's response very accurately.

Tools for analysis of Physical Unclonable Functions

Design and implementation of a hybrid XOR-based Arbiter Physical Unclonable Function (PUF) on FPGA, followed by ASIC synthesis , enabling lightweight and secure hardware authentication with enhanced uniqueness, entropy, and reliability.

Simple Arbiter PUF Implemented in FPGA

This project focuses on enhancing cybersecurity in Operational Technology (OT) systems by analyzing and predicting XOR-based Physical Unclonable Functions (PUFs) using Support Vector Machines (SVMs). By understanding XOR-PUF behavior, we aim to improve the security of OT systems against potential threats.

Assignment submissions for the course CS771A "Introduction to Machine Learning" at IIT-K in 2022-23 II Sem.

GDE PUF Authentication app

Implementation of a Ring Oscillator-based Physically Unclonable Function (PUF) in Sky130, with 8 bits of Challenge-Response Pairs (CRP)

This is a tool for testing the PUF against Modelling attack

Ring oscillator and its application as Physical Unclonable Function (PUF) for password management

Machine Learning Attack on Majority Based Arbiter Physical Unclonable Functions (PUFs)

Decay-based DRAM PUF for the Raspberry Pi 3B+ implemented on top of rpi-open-firmware

SRAM PUF on a microprocessor

Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs