YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 - A Size-Optimized RISC-V CPU
The USRP™ Hardware Driver Repository
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Verilog Ethernet components for FPGA implementation
Hardware abstraction library
HDL libraries and projects
An Open-source FPGA IP Generator
RTL, Cmodel, and testbench for NVDLA