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Please do not submit a Pull Request via github. Our project makes use of
mailing lists for patch submission and review. For more details please
see https://u-boot.readthedocs.io/en/latest/develop/sending_patches.html

The only exception to this is in order to trigger a CI loop on Azure prior
to posting of patches.

Alice Guo and others added 8 commits December 8, 2025 15:01
Replace CONFIG_DISTRO_DEFAULTS with CONFIG_BOOTSTD_FULL to enable the
standard boot framework and use standard boot on i.MX8ULP.

Update CONFIG_BOOTCOMMAND to run bootflow scan before falling back to
board-specific bootcmd, and remove legacy distro boot environment from
imx8ulp_evk.h since bootstd now handles boot targets.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Add board-specific environment variables to imx8ulp_evk.env for better
maintainability. Define bsp_bootcmd in the environment to resolve the
runtime error: "bsp_bootcmd" not defined.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Enable OF_UPSTREAM for i.MX8ULP EVK so that devicetree imported from
Linux kernel release can be used.

If mailbox@29220000 is enabled, gd->arch.ele_dev will be set to this
device for communication with ELE firmware. This is incorrect because
mu@27020000 is the MU used for communication with the ELE firmware. To
prevent misconfiguration, disable mailbox@29220000.

The driver model for watchdog timer is not enabled yet, so disable wdog3
temporarily.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
When doing port reset, the PR bit of PORTSC1 will be automatically
cleared by our IP, but standard EHCI needs explicit clear by software.
The EHCI-HCD driver follow the EHCI specification, so after 50ms wait,
it clear the PR bit by writting to the PORTSC1 register with value
loaded before setting PR.

This sequence is ok for our IP when the delay time is exact. But when
the timer is slower, some bits like PE, PSPD have been set by controller
automatically after the PR is automatically cleared. So the writing to
the PORTSC1 will overwrite these bits set by controller. And eventually
the driver gets wrong status.

We implement the powerup_fixup operation which delays 50ms and will
check the PR until it is cleared by controller. And will update the reg
value which is written to PORTSC register by EHCI-HCD driver. This is
much safer than depending on the delay time to be accurate and aligining
with controller's behaiver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
…to_noparent()

Replace fdtdec_get_addr() with fdtdec_get_addr_size_auto_noparent() so
that address and size are decoded according to the device tree’s
actual #address-cells and #size-cells.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
The i.MX8ULP shares the same USB OTG and PHY controllers as the
i.MX7ULP. Update the driver to support i.MX8ULP.

i.MX8ULP uses the property phys for the phandle of the USB PHY connected
to the port.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Remove the use of CONFIG_USB_MAX_CONTROLLER_COUNT in
enable_usboh3_clk(), as this option is relevant for non-DM USB. The
i.MX8ULP platform uses DM-based USB, so this dependency is unnecessary.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Update the i.MX8ULP EVK device tree files and defconfig to enable the
second USB controller (base address 0x29920000) on i.MX8ULP EVK in host
mode.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
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