Reconfigurable Computing Lab, DESE, Indian Institiute of Science

An implementation of the CORDIC algorithm in Verilog.

Simple 8-bit UART realization on Verilog HDL.

A simple implementation of a UART modem in Verilog.

Verilog AXI components for FPGA implementation

A Verilog implementation of a processor cache.

A collection of URLs related to High Level Synthesis (HLS).

This repository contains the design files of RISC-V Single Cycle Core