Semantic version control => entity-level diffs, blame, and impact analysis on top of git. 26 languages via tree-sitter. Built for coding agents.

Bringing e-graphs to MLIR, natively.

An experimental hardware compiler

Fully defined liberty (std. cells in VLSI) data structure, efficient parser & formatter

The Standard Interface for Incremental Satisfiability Solving

EquivFusion: Unifying Formal Verification from Algorithms to Netlists for High-Efficiency Signoff

Research paper based on or related to ABC.

A Python library for working with logic networks, synthesis, and optimization.

Python library that provides methods for Boolean circuit manipulation, analysis, and synthesis

EPFL logic synthesis benchmarks

SystemVerilog language server

C++ logic network library

RePlAce global placement tool

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

ABC: System for Sequential Logic Synthesis and Formal Verification

Vitis Libraries

RISC-V CPU implementation in Amaranth HDL (aka nMigen)

Tenstorrent MLIR compiler

[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

BTOR2 MLIR project

Experimental MLIR Rust compiler

A framework for writing FPGA firmware using the Rust Programming Language

Communication framework for RTL simulation and emulation.

A compiler for homomorphic encryption

Stable diffusion dedicated Hardware with multiple pipelined processor cores

Inference Llama 2 in one file of pure 🔥