Github: http://github.com/ultraembedded/riscv

A 32-bit RISC-V core written in Verilog and an instruction set simulator supporting RV32IM.
This core has been tested against a co-simulation model and exercised on FPGA.

For a higher performance dual issue CPU with branch prediction, see my latest RISC-V core here; http://github.com/ultraembedded/biriscv

• 32-bit RISC-V ISA CPU core.
• Support RISC-V integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
• Supports user, supervisor and machine mode privilege levels.
• Basic MMU support - capable of booting Linux with atomics (RV-A) SW emulation.
• Implements base ISA spec v2.1 and privileged ISA spec v1.11.
• Verified using Google's RISCV-DV random instruction sequences using cosimulation against C++ ISA model.
• Support for instruction / data cache, AXI bus interfaces or tightly coupled memories.
• Configurable number of pipeline stages and result forwarding options.
• Synthesizable Verilog 2001, Verilator and FPGA friendly.
• Coremark: 2.94 CoreMark/MHz
• Dhrystone: 1.25 DMIPS/MHz ('legal compile options' / 337 instructions per iteration)
• Want higher performance (4.1CM/MHz / 1.9DMIPS/MHz) - see my improved core.

The top (top_tcm_axi/src_v/riscv_tcm_top.v) contains;

• Instances one of the above cores, adding RAM and standard bus interfaces.
• 64KB dual ported RAM for (I/D code and data).
• AXI4 slave port for loading the RAM, DMA access, etc (including support for burst access).
• AXI4-Lite master port for CPU access to peripherals.
• Separate reset for CPU core to dual ported RAM / AXI interface (to allow program code to be loaded prior to CPU reset de-assertion).

A basic System-C / Verilator based testbench for the core is provided.

Dependencies;

• gcc
• make
• libelf
• System-C (specify path using SYSTEMC_HOME)
• Verilator (specify path using VERILATOR_SRC)

To build the testbench;

cd top_tcm_axi/tb
make

To run the provided test executable;

cd top_tcm_axi/tb
make run

The top (top_cache_axi/src_v/riscv_top.v) contains;

• Instances one of the above cores, adding RAM and standard bus interfaces.
• 16KB 2-way set associative instruction cache
• 16KB 2-way set associative data cache with write-back and allocate on write.
• 2 x AXI4 master port for CPU access to instruction / data / peripherals.