RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
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rv32im
Here are 43 public repositories matching this topic...
A self-hosting and educational C optimizing compiler
c linux arm compiler riscv qemu armv7 cross-compiler elf self-hosting risc-v compiler-optimization rv32i rv32im ssa-form
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Apr 11, 2026 - C
32-bit Superscalar RISC-V CPU
linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors
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Sep 18, 2021 - Verilog
Trivial RISC-V Linux binary bootloader
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Apr 3, 2021 - C
A web-based RISC-V simulator https://riscv-simulator-five.vercel.app
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Jan 22, 2026 - TypeScript
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
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May 10, 2020 - Verilog
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor
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Feb 19, 2025 - Verilog
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWa…
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Oct 31, 2021 - Verilog
A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)
cpu fpga runtime architecture riscv verilog uart systemverilog hdl microarchitecture branch-prediction coremark rv32i cpu-architecture dhrystone rv32im uart-programming
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Mar 11, 2026 - SystemVerilog
A minimalist monolithic OS kernel for the RISC-V 32-bit architecture. An educational project demonstrating core concepts like multitasking, virtual memory, and system calls.
c kernel llvm operating-system qemu virtual-memory multitasking risc-v educational-project rv32im monolithic-kernel
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Jan 7, 2026 - C
RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.
python jenkins cpu processor verification dpi spike riscv isa vcs systemverilog uvm constrained-random sva rv32im questa functional-coverage
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Aug 20, 2025 - SystemVerilog
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