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Verilog 46 29 Updated Sep 13, 2024

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

C++ 62 11 Updated Apr 8, 2026

Verilog to Routing -- Open Source CAD Flow for FPGA Research

C++ 1,216 440 Updated Apr 14, 2026

The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fa…

C++ 38 11 Updated Jul 22, 2025

A Simple VNC + SSH Shell + SFTP Client

JavaScript 192 16 Updated Dec 15, 2025

Website for Verilog to Routing

SCSS 6 3 Updated Apr 8, 2026

Parsing library for BLIF netlists

C++ 19 11 Updated Nov 1, 2024

Buildbot Infrastructure for VTR

HTML 6 5 Updated Dec 12, 2019
C++ 10 8 Updated Nov 13, 2025