Verilator open-source SystemVerilog simulator and lint system

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Send video/audio over HDMI on an FPGA

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

VeeR EH1 core

A directory of Western Digital’s RISC-V SweRV Cores

The root repo for lowRISC project and FPGA demos.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

VeeR EL2 Core

A simple RISC V core for teaching

Open hardware test equipment

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

Hardware implementation of the PJDL protocol.

My second attempt at a RISC-V CPU with learnings form my previous attempt.

PJON hardware integrated into the Croc SoC