Verilog Ethernet components for FPGA implementation

SERV - The SErial RISC-V CPU

The Ultra-Low Power RISC-V Core

An open source GPU based off of the AMD Southern Islands ISA.

32-bit Superscalar RISC-V CPU

3-stage RV32IMACZb* processor with debug

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

A tiny Open POWER ISA softcore written in VHDL 2008

Verilog I2C interface for FPGA implementation

RISC-V Formal Verification Framework

Open source retro ISA video card

VRoom! RISC-V CPU

current focus on Colorlight i5 and i9 & i9plus module

An attempt to recreate the RP2040 PIO in an FPGA

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Open-source electrophoretics display controller. Mirror of https://gitlab.com/zephray/caster

Traces, schematics, and general infos about custom chips reverse-engineered from silicon

OpenRISC 1200 implementation

Support files for participating in a Fomu workshop

IceChips is a library of all common discrete logic devices in Verilog

Vortex Graphics

An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA

A Sound Blaster compatible sound card for Micro Channel bus computers

Isle FPGA Computer

PCXT port for MiSTer by spark2k06.

5-stage RISC-V CPU, originally developed for RISCBoy

Low-area DVI experiment for iCE40 UP5k and HX1k FPGAs

M-extension for RISC-V cores.