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written in Verilog
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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
PicoRV32 RISC-V project for Tang Nano 20K FPGA development board
The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)
Simple SoC using PicoRV32 RISC-V soft core on the Tang Nano 9K and 20K FPGA development boards
A Z80 verilog project for Lattice FPGA using VSCode. With the function of automated installation Toolchain
Projects related to the serv RISC-V core on FPGAs including the servant SoC using Gowin FPGA tools
Z80 + USB + TinyFPGA-BX in Verilog using open-source Yosys+NextPNR