Verilog UART DPI module

RISC-V architecture concurrency model litmus tests

A minimal UDP stack based on DPDK

Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level

OpenSoC Fabric - A Network-On-Chip Generator

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

SystemC/TLM-2.0 Co-simulation framework

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)

RISC-V SystemC-TLM simulator

Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-processor performance of central processing units (CPU) and embed…

Random instruction generator for RISC-V processor verification

Patches & Script for AOSP to run on Xuantie RISC-V CPU

Extrinsic Calibration of a Odom and 2d Laser

ROS-Industrial Universal Robots support (https://wiki.ros.org/universal_robot)

Support for Rocket Chip on Zynq FPGAs

Stanford Doggo is an open source quadruped robot that jumps, flips, and trots!

Open-source high-performance RISC-V processor

RISC-V Open Source Supervisor Binary Interface

RISC-V Proxy Kernel

Here is everything you need to know about POPI, our open-source quadruped robot. If you want to check the videos we will release about it, you can have a look at our YouTube channel.

Visualization of Motions for Legged Robots in ros-rviz

A light-weight, Eigen-based C++ library for trajectory optimization for legged robots.

MIT Cheetah I Implementation

An Architecture for the Versatile Control of Legged Robots

Freedom U Software Development Kit (FUSDK)

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro