Stars
An awesome list of self-driving cars
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
IC design and development should be faster，simpler and more reliable
A directory of Western Digital’s RISC-V SweRV Cores
OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
OpenSoC Fabric - A Network-On-Chip Generator
Black-box Optimizer based on Bayesian Optimization
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
RTL Verilog library for various DSP modules
This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.
an intermediate representation for continuously reconfigurable hardware
A Linux-capable RISC-V multicore for and by the world
Curated coding interview preparation materials for busy software engineers
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Paper list of multi-agent reinforcement learning (MARL)
A hardware implementation of a feed-forward Convolutional Neural Network called XNOR-Net which has faster execution due to the replacement of vector-matrix multiplication to “XNOR + Popcount” opera…
BaseJump STL: A Standard Template Library for SystemVerilog
SCR1 is a high-quality open-source RISC-V MCU core in Verilog