符合nature论文学术表达和科研绘图的Skill

CORE-V Family of RISC-V Cores

A FPGA friendly 32 bit RISC-V CPU implementation

SERV - The SErial RISC-V CPU

Elevate your AI research writing, no more tedious polishing ✨

OpenXuantie - OpenC910 Core

OpenXuantie - OpenE902 Core

VeeR EH1 core

IC design and development should be faster，simpler and more reliable

奔跑吧linux内核第二版（卷1，卷2，入门篇） 实验平台

32-bit Superscalar RISC-V CPU

Open Source Chip Project by University (OSCPU) - Zhoushan Core

RISC-V Cores, SoC platforms and SoCs

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

Don't Starve Together server panel. Manage room with ease, featuring visual world and mod management, player log collection。饥荒联机服务器面板。轻松管理房间，支持可视化的世界和模组管理，玩家日志采集

RISC-V Debug Support for our PULP RISC-V Cores

cadence flow for genus and innovus with UPF added.

RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.

🛠️ ❤️ Want to know NixOS & Flakes in detail? Looking for a beginner-friendly tutorial? Then you've come to the right place! 想要学习使用 NixOS 与 Flakes 吗？在寻找一份新手友好的教程？那你可来对地方了！

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

SonicBOOM: The Berkeley Out-of-Order Machine

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

An FPGA-based USB 1.1 (full-speed) device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB 1.1 (full-sp…

USB 2.0 FS Device controller IP core written in SystemVerilog

USB 2.0 Device IP Core

Tiny Tapeout GDS Action (using LibreLane)