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Starred repositories

13 results for source starred repositories written in Verilog
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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,837 884 Updated Jun 27, 2024

current focus on Colorlight i5 and i9 & i9plus module

Verilog 323 66 Updated Nov 5, 2025

Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation

Verilog 289 46 Updated Feb 11, 2024

Example designs showing different ways to use F4PGA toolchains.

Verilog 281 79 Updated Mar 27, 2024

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Verilog 258 49 Updated Aug 21, 2023

Public examples of ICE40 HX8K examples using Icestorm

Verilog 110 22 Updated Apr 24, 2023

This is a simple UART echo test for the iCEstick Evaluation Kit

Verilog 39 7 Updated Dec 30, 2018
Verilog 37 9 Updated Apr 4, 2015

Implementing a RISC-V CPU on FPGA(Cyclone II)

Verilog 22 3 Updated Feb 19, 2023

FPGA bitcoin miner for the Lattice ECP5 evaluation board.

Verilog 9 2 Updated Apr 2, 2022

UART + UART packets encoding/decoding + pc reader program for Lattice icestick

Verilog 4 Updated Oct 17, 2021

Submodule-collection of open source toolchain for Lattice ICE FPGAs (and other)

Verilog 2 Updated Aug 28, 2025

Example project for Lattice icestick fpga

Verilog 1 Updated Oct 14, 2021