The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Bus bridges and other odds and ends

🚀🚀🚀 A collection of some awesome public YOLO object detection series projects.

DC-SCM LTPI Reference Implementation

MPSoC architecture for accelerating drone components and interfacing with ROS2.

All You Need to Know About QDMA

Tutorials based on the ASL (American Sign Language) dataset

Arrow Global solution based on iMX8M MPU for Human Machine Interface Applications

A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit.

CSV spreadsheets and other material for AI accelerator survey papers

Open source machine learning accelerators

Compiler for Neural Network hardware accelerators

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Tengine is a lite, high performance, modular inference engine for embedded device

FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor.

A voxel game/Minecraft clone for the iCE40 UP5K FPGA

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Sample code for AIdea FPGA Edge AI – AOI Defect Classification competition

The evaluation system (referee) for the 2020 Low Power Computer Vision Challenge.

OpenDLA for trying the demo and FPGA solution

A curated list of radar datasets, detection, tracking and fusion

VNx: Vitis Network Examples

implementation of paper - You Only Learn One Representation: Unified Network for Multiple Tasks (https://arxiv.org/abs/2105.04206)

A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard