Skip to content
View xmitman's full-sized avatar

Block or report xmitman

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Starred repositories

17 stars written in Verilog
Clear filter

An FPGA-based NFC (RFID) reader with a simple circuit rather than RFID chips. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器,不需要专门的RFID芯片。

Verilog 142 26 Updated Jan 26, 2024

FPGA based transmitter

Verilog 99 15 Updated Apr 14, 2017

FPGA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit

Verilog 80 20 Updated Jan 5, 2024

Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit

Verilog 59 13 Updated Jan 30, 2020

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

Verilog 58 12 Updated Jun 6, 2020

Tools for working with the 802.11B scrambler when writing Packet-in-Packet exploits.

Verilog 20 7 Updated Sep 15, 2013

iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter

Verilog 18 1 Updated Nov 24, 2025

WPA-PSK cracking for FPGA devices

Verilog 18 5 Updated May 3, 2017

Simple voltage glitcher implementation for the iCEBreaker FPGA board

Verilog 18 5 Updated Mar 2, 2020

Trojan Hardware implemented in the OpenCores Amber ARM Core

Verilog 7 2 Updated Mar 17, 2014

Hardware designs for fault correction

Verilog 4 1 Updated Dec 8, 2019

Mitigating SAT attack by integrating Anti-SAT block into a locked circuit

Verilog 3 Updated Jan 4, 2021

Voltage glitcher implemented on Lattice MachXO3L FPGA

Verilog 3 Updated Mar 25, 2024

glitcher

Verilog 2 Updated Jan 28, 2025

A system, using Altera Cyclone IV's (and potentially other chips') PLL(s) to produce a variable frequency clock that sweeps a range of 100 MHz - ~500MHz with 1MHz resolution

Verilog 2 1 Updated Jul 7, 2017
Verilog 2 Updated Aug 17, 2015

Hardware MITM attacks on bus communication using FPGA. (Master's thesis)

Verilog 1 Updated Jun 3, 2025