This project evaluates the acceleration of softmax using RVV vector intrinsics. The result shows up to 99% execution time can be reduced by replacing glibc’s scalar expf() with a Taylor-approximate…

IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.

Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Data

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably …

A High-performance Timing Analysis Tool for VLSI Systems

Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Wrapped, but for Weekly Reports

Yosys Open SYnthesis Suite

Input / Output Physical Memory Protection Unit for RISC-V

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

A matrix extension proposal for AI applications under RISC-V architecture

Simple runtime for Pulp platforms