- 👋 Hi, I’m @yash-jangra
- 👀 I’m interested in technology, traveling.
- 🌱 I’m currently exploring the intersection of robotics and IoT.
- 📫 How to reach me: Email- yjangra2002@gmail.com LinkedIn- https://www.linkedin.com/in/yash-jangra-96a21615b/
- Delhi
-
16:36
(UTC +05:30)
Popular repositories Loading
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Team-Razor-Crest
Team-Razor-Crest PublicSolution submission for Round-1 of the Tryst Autobot Challenge
Jupyter Notebook 1
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-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture-
-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture- PublicForked from Mostafa-Hassanien/-A-32-bit-5-stage-Pipelined-MIPS-based-RISC-Core-based-on-Harvard-Architecture-
This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Archit…
Verilog 1
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8bit_synchronous_fifo_design
8bit_synchronous_fifo_design PublicVerilog implementation of an 8-bit Synchronous FIFO (First-In-First-Out) memory module
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Hacktoberfest
Hacktoberfest PublicThis repo is my personal project for showcasing my photographs that I click and edit.
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