- 👋 Hi, I’m @yegane-AI. You can call me Ariana!
- 👀 I’m interested in Computer Architecture and Hardware Security.
- 🌱 I’m currently learning Parallel programming, and logic locking methods.
- 💞️ I’m looking to collaborate on hardware verification.
- 📫 How to reach me: send an email to pardis.m74@gmail.com
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RISC-V-Simulation
RISC-V-Simulation PublicIn this repo, I keep working on a 7-stage pipeline RISC-V simulator. Suggestions to improve this project is highly appreciated.
C++
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UVM-Protocols
UVM-Protocols PublicIn this repo, I put the Universal Verification Methodology (UVM) test benches for data movement protocols
SystemVerilog
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cars-lab-repo/CoLA
cars-lab-repo/CoLA PublicCNN Model for Secure Low Overhead Logic Locking Assignment
Jupyter Notebook 1
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Low-Power-System-Design
Low-Power-System-Design PublicIn this repository, I'll add the codes and programs I wrote whether as assignments or exams for the fault-tolerant system design.
SourcePawn
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