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yegane-AI/README.md
  • 👋 Hi, I’m @yegane-AI. You can call me Ariana!
  • 👀 I’m interested in Computer Architecture and Hardware Security.
  • 🌱 I’m currently learning Parallel programming, and logic locking methods.
  • 💞️ I’m looking to collaborate on hardware verification.
  • 📫 How to reach me: send an email to pardis.m74@gmail.com

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  1. RISC-V-Simulation RISC-V-Simulation Public

    In this repo, I keep working on a 7-stage pipeline RISC-V simulator. Suggestions to improve this project is highly appreciated.

    C++

  2. UVM-Protocols UVM-Protocols Public

    In this repo, I put the Universal Verification Methodology (UVM) test benches for data movement protocols

    SystemVerilog

  3. cars-lab-repo/CoLA cars-lab-repo/CoLA Public

    CNN Model for Secure Low Overhead Logic Locking Assignment

    Jupyter Notebook 1

  4. specweaver specweaver Public

    Python

  5. Low-Power-System-Design Low-Power-System-Design Public

    In this repository, I'll add the codes and programs I wrote whether as assignments or exams for the fault-tolerant system design.

    SourcePawn

  6. cf_ai_hardware_debug_assistant cf_ai_hardware_debug_assistant Public

    TypeScript 1 1