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7 results for source starred repositories written in Verilog
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PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,761 871 Updated Jun 27, 2024

SERV - The SErial RISC-V CPU

Verilog 1,666 231 Updated Oct 17, 2025

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

Verilog 1,577 354 Updated Aug 9, 2025

OpenXuantie - OpenC910 Core

Verilog 1,339 356 Updated Jun 28, 2024

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilog 594 79 Updated Oct 28, 2025

PanoLogic Zero Client G1 reverse engineering info

Verilog 75 12 Updated Apr 2, 2024

Simple "Hello World" base project for Pano Logic G1

Verilog 6 Updated Nov 14, 2019