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Verilator open-source SystemVerilog simulator and lint system
OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
RSD: RISC-V Out-of-Order Superscalar Processor
A Linux-capable RISC-V multicore for and by the world
Contains the code examples from The UVM Primer Book sorted by chapters.
Test suite designed to check compliance with the SystemVerilog standard.
Source code repo for UVM Tutorial for Candy Lovers
AIA IP compliant with the RISC-V AIA spec
SystemVerilog Functional Coverage for RISC-V ISA
Using Nim to interface with SystemVerilog test benches via DPI-C
Simple UVM environment for experimenting with Verilator.
Simple template-based UVM code generator
Test dashboard for verification features in Verilator
CORE-V MCU UVM Environment and Test Bench
🇯 JSON encoder and decoder in pure SystemVerilog
This is the last (6th) project of the Digital System course at the university. In this project, I have implemented a complete multiplier base on IEEE 754-2019 using SystemVerilog HDL(Hardware Descr…
MsgPack_SV is a UVM compatible SystemVerilog implementation of an encoder and decoder for the MessagePack serialization format.