Statically scheduled Neural Processing Unit

Configurable low-precision floating-point and microscaling hardware in Chisel

Generating Schedules for Robotic Workloads

Software kernels for the Radiance GPU

Functional model for Radiance

MLIR-in as a compiler stack for ucb-bar

Verilog hardware abstraction library

SP26 Floating Point Units Generator

A simple perf model for NPU.

This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo prepared and delivered by Prof. Adam (Adi) Teman.

CUDA Tile IR is an MLIR-based intermediate representation and compiler infrastructure for CUDA kernel optimization, focusing on tile-based computation patterns and optimizations targeting NVIDIA te…

Allo Accelerator Design and Programming Framework (PLDI'24)

A hardware–software co-design framework for developing and characterizing extended reality (XR) workloads on embedded systems-on-chip (SoCs).

EE194 Lab 0: Chisel Crash Course

Lab manual EECS151 Tapeout Decal. Public view - release to main branch only once ready.

A machine learning accelerator core designed for energy-efficient AI at the edge.

Model-predictive control for microcontrollers (fork mapping tinyMPC to gemmini or other HW accelerators)

A Heterogeneous GPU Platform for AI and Neural Graphics

Autocomp: Optimize any AI kernel, anywhere.

A submodule of Chipyard https://github.com/ucb-bar/chipyard

An open-source UCIe implementation

Cluster-level matrix unit integration into GPUs, implemented in Chipyard SoC

Chisel RISC-V Vector 1.0 Implementation

Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.

LLM training in simple, raw C/CUDA