Skip to content
View zym0707's full-sized avatar

Block or report zym0707

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
3 stars written in Verilog
Clear filter

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Verilog 2,792 1,042 Updated Mar 24, 2021

IC design and development should be faster,simpler and more reliable

Verilog 1,975 591 Updated Dec 31, 2021

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

Verilog 93 29 Updated Sep 20, 2023