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Starred repositories

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A conda-forge distribution.

Shell 9,882 511 Updated Jun 3, 2026

The official repository for the gem5 computer-system architecture simulator.

C++ 2,657 1,864 Updated Jun 12, 2026

A comprehensive list of papers using large language/multi-modal models for Robotics/RL, including papers, codes, and related websites

4,399 334 Updated Apr 9, 2026

The world's largest GitHub Repository for LLMs + Robotics

850 60 Updated Jul 14, 2024

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Batchfile 819 160 Updated Sep 14, 2023

Kernel source tree for Raspberry Pi-provided kernel builds. Issues unrelated to the linux kernel should be posted on the community forum at https://forums.raspberrypi.com/

C 12,943 5,423 Updated Jun 12, 2026

A complete computer science study plan to become a software engineer.

351,292 83,430 Updated Aug 28, 2025

SystemVerilog to Verilog conversion

Haskell 736 64 Updated Mar 28, 2026

A minimal GPU design in Verilog to learn how GPUs work from the ground up

SystemVerilog 12,573 1,199 Updated Aug 18, 2024
C++ 39 10 Updated Nov 8, 2023

Contains the source code examples described in the "Intel® 64 and IA-32 Architectures Optimization Reference Manual"

Assembly 810 89 Updated May 3, 2024

This may be the simplest implement of DDPM. You can directly run Main.py to train the UNet on CIFAR-10 dataset and see the amazing process of denoising.

Python 2,178 218 Updated Apr 24, 2023

SDN网络指南(SDN Handbook)

C 1,528 426 Updated Apr 30, 2024

100 Days of RTL

SystemVerilog 418 113 Updated Aug 15, 2024

Convert CAJ (China Academic Journals) files to PDF. 转换中国知网 CAJ 格式文献为 PDF。佛系转换,成功与否,皆是玄学。

Python 3,223 641 Updated Mar 20, 2024

Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

380 122 Updated Mar 27, 2023

Verilog AXI components for FPGA implementation

Verilog 2,071 533 Updated Feb 27, 2025

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

SystemVerilog 206 71 Updated Jun 10, 2026

RISC-V Formal Verification Framework

Verilog 632 104 Updated Apr 6, 2022

数字IC相关资料

1,480 361 Updated Jul 1, 2025

4 stage, in-order, secure RISC-V core based on the CV32E40P

SystemVerilog 160 30 Updated Oct 31, 2024

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

SystemVerilog 133 32 Updated Jul 11, 2025

OpenSource HummingBird RISC-V Software Development Kit

C 175 55 Updated Dec 5, 2023

The Ultra-Low Power RISC-V Core

Verilog 1,856 429 Updated Aug 6, 2025

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Verilog 624 145 Updated Mar 15, 2018

AMBA AXI VIP

SystemVerilog 466 125 Updated Jun 28, 2024

AMBA bus lecture material

Verilog 534 141 Updated Jan 21, 2020

Fourier Domain Adaptation for Semantic Segmentation

Python 554 87 Updated Jul 1, 2020
108 31 Updated Jan 27, 2021
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