®

PGA204
PGA205

Programmable Gain
INSTRUMENTATION AMPLIFIER

FEATURES DESCRIPTION
● DIGITALLY PROGRAMMABLE GAIN: The PGA204 and PGA205 are low cost, general pur-
pose programmable-gain instrumentation amplifiers
PGA204: G=1, 10, 100, 1000V/V
PGA205: G=1, 2, 4, 8V/V offering excellent accuracy. Gains are digitally se-
lected: PGA204—1, 10, 100, 1000, and PGA205—1,
● LOW OFFSET VOLTAGE: 50µV max 2, 4, 8V/V. The precision and versatility, and low cost
● LOW OFFSET VOLTAGE DRIFT: 0.25µV/°C of the PGA204 and PGA205 make them ideal for a
● LOW INPUT BIAS CURRENT: 2nA max wide range of applications.
Gain is selected by two TTL or CMOS-compatible
● LOW QUIESCENT CURRENT: 5.2mA typ
address lines, A0 and A1. Internal input protection can
● NO LOGIC SUPPLY REQUIRED withstand up to ±40V on the analog inputs without
● 16-PIN PLASTIC DIP, SOL-16 PACKAGES damage.
The PGA204 and PGA205 are laser trimmed for very
APPLICATIONS low offset voltage (50µV), drift (0.25µV/°C) and high
common-mode rejection (115dB at G=1000). They op-
● DATA ACQUISITION SYSTEM erate with power supplies as low as ±4.5V, allowing use
● GENERAL PURPOSE ANALOG BOARDS in battery operated systems. Quiescent current is 5mA.
● MEDICAL INSTRUMENTATION The PGA204 and PGA205 are available in 16-pin
plastic DIP, and SOL-16 surface-mount packages, speci-
fied for the –40°C to +85°C temperature range.

VO1 V+
1 13
PGA204
– 4 Over-Voltage
VIN PGA205
Protection Feedback
A1
12
25kΩ 25kΩ

16
A1 Digitally Selected
15 A3 VO
A0 Feedback Network 11
14
Digital
Ground

A2 Ref
+ 5 Over-Voltage 10
VIN 25kΩ 25kΩ
Protection

6 7 9 8

VOS Adj VO2 V–

International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®

©
1991 Burr-Brown Corporation 1
PDS-1176A PGA204/205
Printed in U.S.A. October, 1993

SBOS022
SPECIFICATIONS
ELECTRICAL PGA204 G=1, 10, 100, 1000V/V
At TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted.

PGA204BP, BU PGA204AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT
Offset Voltage, RTI TA=+25°C ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV
vs Temperature TA=TMIN to TMAX ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°C
vs Power Supply VS=±4.5V to ±18V 0.5+2/G 3+10/G * * µV/V
Long-Term Stability ±0.2+0.5/G * µV/mo
Impedance, Differential 1010||6 * Ω || pF
Common-Mode 1010||6 * Ω || pF
Input Common-Mode Range VO=0V (see text) ±10.5 ±12.7 * * V
Safe Input Voltage ±40 * V
Common-Mode Rejection VCM=±10V, ∆RS=1kΩ
G=1 80 99 75 90 dB
G=10 96 114 90 106 dB
G=100 110 123 106 110 dB
G=1000 115 123 106 110 dB
BIAS CURRENT ±0.5 ±2 * ±5 nA
vs Temperature ±8 * pA/°C
Offset Current ±0.5 ±2 * * nA
vs Temperature ±8 * pA/°C
NOISE, Voltage, RTI(1): f=10Hz G≥100, RS=0Ω 16 * nV/√Hz
f=100Hz G≥100, RS=0Ω 13 * nV/√ Hz
f=1kHz G≥100, RS=0Ω 13 * nV/√Hz
fB=0.1Hz to 10Hz G≥100, RS=0Ω 0.4 * µVp-p
Noise Current
f=10Hz 0.4 * pA/√Hz
f=1kHz 0.2 * pA/√Hz
fB=0.1Hz to 10Hz 18 * pAp-p
GAIN, Error G=1 ±0.005 ±0.024 * ±0.05 %
G=10 ±0.01 ±0.024 * ±0.05 %
G=100 ±0.01 ±0.024 * ±0.05 %
G=1000 ±0.02 ±0.05 * ±0.1 %
Gain vs Temperature G=1 to 1000 ±2.5 ±10 * * ppm/°C
Nonlinearity G=1 ±0.0004 ±0.001 * ±0.002 % of FSR
G=10 ±0.0004 ±0.002 * ±0.004 % of FSR
G=100 ±0.0004 ±0.002 * ±0.004 % of FSR
G=1000 ±0.0008 ±0.01 * ±0.02 % of FSR
OUTPUT
Voltage, Positive(2) IO=5mA, TMIN to TMAX (V+)–1.5 (V+)–1.3 * * V
Negative(2) IO=–5mA, TMIN to TMAX (V–)+1.5 (V–)+1.3 * * V
Load Capacitance Stability 1000 * pF
Short Circuit Current +23/–17 * mA
FREQUENCY RESPONSE
Bandwidth, –3dB G=1 1 * MHz
G=10 80 * kHz
G=100 10 * kHz
G=1000 1 * kHz
Slew Rate VO=±10V, G=10 0.3 0.7 * * V/µs
Settling Time(3), 0.1% G=1 22 * µs
G=10 23 * µs
G=100 100 * µs
G=1000 1000 * µs
0.01% G=1 23 * µs
G=10 28 * µs
G=100 140 * µs
G=1000 1300 * µs
Overload Recovery 50% Overdrive 70 * µs
DIGITAL LOGIC
Digital Ground Voltage, VDG V– (V+)–4 * * V
Digital Low Voltage V– VDG+0.8V * * V
Digital Input Current 1 * µA
Digital High Voltage VDG +2 V+ * * V
POWER SUPPLY, Voltage ±4.5 ±15 ±18 * * * V
Current VIN=0V +5.2/–4.2 ±6.5 * ±7.5 mA
TEMPERATURE RANGE
Specification –40 +85 * * °C
Operating –40 +125 * * °C
θJA 80 * °C/W

* Specification same as PGA204BP.

NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes
time to switch to a new gain.
®

PGA204/205 2
SPECIFICATIONS
ELECTRICAL PGA205 G=1, 2, 4, 8V/V
At TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted.

PGA205BP, BU PGA205AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
INPUT
Offset Voltage, RTI TA=+25°C ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV
vs Temperature TA=TMIN to TMAX ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°C
vs Power Supply VS=±4.5V to ±18V 0.5+2/G 3+10/G * * µV/V
Long-Term Stability ±0.2+0.5/G * µV/mo
Impedance, Differential 1010||6 * Ω||pF
Common-Mode 1010||6 * Ω||pF
Input Common-Mode Range VO=0V (see text) ±10.5 ±12.7 * * V
Safe Input Voltage ±40 * V
Common-Mode Rejection VCM=±10V, ∆RS=1kΩ
G=1 80 94 75 88 dB
G=2 85 100 80 94 dB
G=4 90 106 85 100 dB
G=8 95 112 89 106 dB
BIAS CURRENT ±0.5 ±2 * ±5 nA
vs Temperature ±8 * pA/°C
Offset Current ±0.5 ±2 * * nA
vs Temperature ±8 * pA/°C
Noise Voltage, RTI(1): f=10Hz G=8, RS=0Ω 19 * nV/√Hz
f=100Hz G=8, RS=0Ω 15 * nV/√Hz
f=1kHz G=8, RS=0Ω 15 * nV/√Hz
fB=0.1Hz to 10Hz G=8, RS=0Ω 0.5 * µVp-p
Noise Current
f=10Hz 0.4 * pA/√Hz
f=1kHz 0.2 * pA/√Hz
fB=0.1Hz to 10Hz 18 * pAp-p
GAIN, Error G=1 ±0.005 ±0.024 * ±0.05 %
G=2 ±0.01 ±0.024 * ±0.05 %
G=4 ±0.01 ±0.024 * ±0.05 %
G=8 ±0.01 ±0.024 * ±0.05 %
Gain vs Temperature G=1 to 8 ±2.5 ±10 * * ppm/°C
Nonlinearity G=1 ±0.00024 ±0.001 * ±0.002 % of FSR
G=2 ±0.00024 ±0.002 * ±0.004 % of FSR
G=4 ±0.00024 ±0.002 * ±0.004 % of FSR
G=8 ±0.00024 ±0.002 * ±0.004 % of FSR
OUTPUT
Voltage, Positive(2) IO=5mA, TMIN to TMAX (V+)–1.5 (V+)–1.3 * * V
Negative(2) IO=–5mA, TMIN to TMAX (V–)+1.5 (V–)+1.3 * * V
Load Capacitance Stability 1000 * pF
Short Circuit Current +23/–17 * mA
FREQUENCY RESPONSE
Bandwidth, –3dB G=1 1 * MHz
G=2 400 * kHz
G=4 200 * kHz
G=8 100 * kHz
Slew Rate VO=±10V, G=8 0.3 0.7 * * V/µs
Settling Time(3), 0.1% G=1 22 * µs
G=2 22 * µs
G=4 23 * µs
G=8 23 * µs
0.01% G=1 23 * µs
G=2 23 * µs
G=4 25 * µs
G=8 28 * µs
Overload Recovery 50% overdrive 70 * µs
DIGITAL LOGIC INPUTS
Digital Ground Voltage, VDG V– (V+)–4 * * V
Digital Low Voltage V– VDG+0.8V * * V
Digital Low Current 1 * µA
Digital High Voltage VDG+2 V+ * * V
POWER SUPPLY, Voltage ±4.5 ±15 ±18 * * * V
Current VIN=0V +5.2/–4.2 ±6.5 * ±7.5 mA
TEMPERATURE RANGE
Specification –40 +85 * * °C
Operating –40 +125 * * °C
θJA 80 * °C/W

* Specification same as PGA204BP.

NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes
time to switch to a new gain.
®

3 PGA204/205
PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS
PACKAGE DRAWING Supply Voltage .................................................................................. ±18V
MODEL PACKAGE NUMBER(1) Analog Input Voltage Range ............................................................. ±40V
PGA204AP 16-Pin Plastic DIP 180 Logic Input Voltage Range .................................................................. ±VS
PGA204BP 16-Pin Plastic DIP 180 Output Short-Circuit (to ground) .............................................. Continuous
PGA204AU SOL-16 Surface Mount 211 Operating Temperature ................................................. –40°C to +125°C
PGA204BU SOL-16 Surface Mount 211 Storage Temperature ..................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
PGA205AP 16-Pin Plaseic DIP 180 Lead Temperature (soldering –10s) .............................................. +300°C
PGA205BP 16-Pin Plastic DIP 180
PGA205AU SOL-16 Surface Mount 211
PGA205BU SOL-16 Surface Mount 211

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.

ORDERING INFORMATION
MODEL GAINS PACKAGE TEMPERATURE RANGE
PGA204AP 1, 10, 100, 1000V/V 16-Pin Plastic DIP –40 to +85°C
PGA204BP 1, 10, 100, 1000V/V 16-Pin Plastic DIP –40 to +85°C
PGA204AU 1, 10, 100, 1000V/V SOL-16 Surface-Mount –40 to +85°C
PGA204BU 1, 10, 100, 1000V/V SOL-16 Surface-Mount –40 to +85°C

PGA205AP 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 to +85°C

PGA205BP 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 to +85°C
PGA205AU 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 to +85°C
PGA205BU 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 to +85°C

PGA204/205 4
DICE INFORMATION

PAD FUNCTION PAD FUNCTION

1 VO1 9 VO2

FPO
2 — 10 Ref
3 — 11 VO
4 V–IN 12 Feedback
5 V+IN 13 V+
6 VOS Adj 14 Dig. Ground
7 VOS Adj 15 A0
8 V– 16 A1
Substrate Bias: Internally connected to V– power supply.

MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 186 x 130 ±5 4.72 x 3.30 ±0.13
Die Thickness 20 ±3 0.51 ±0.08
Min. Pad Size 4x4 0.1 x 0.1
Backing Gold

PGA204/205 DIE TOPOGRAPHY

PIN CONFIGURATION ELECTROSTATIC

Top View
DISCHARGE SENSITIVITY
VO1 1 16 A1
This integrated circuit can be damaged by ESD. Burr-Brown
NC 2 15 A0 recommends that all integrated circuits be handled with ap-
NC 3 14 Dig. Ground propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
V–IN 4 13 V+
ESD damage can range from subtle performance degradation
V+IN 5 12 Feedback
to complete device failure. Precision integrated circuits may
VOS Adjust 6 11 VO be more susceptible to damage because very small parametric
VOS Adjust 7 10 Ref changes could cause the device not to meet its published
specifications.
V– 8 9 VO2

NC: No Internal Connection.

5 PGA204/205
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VS = ±15V, unless otherwise noted.

GAIN vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY

140
G = 1k,100
G=1k

Common-Mode Rejection (dB)

G = 10
1k 120

G=100 “B” Grade

Gain (V/V)

100 100 G=1 G = 1k

G=10
10 80 G = 100

G=1
1 60 G = 10

G=1
40
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

INPUT COMMON-MODE VOLTAGE RANGE POSITIVE POWER SUPPLY REJECTION

vs OUTPUT VOLTAGE vs FREQUENCY
15 140
y A1 Limit
ed b + Ou ed by A
Limit ut Swing tput 120
t p Swin2
Power Supply Rejection (dB)

10 u
Common-Mode Voltage (V)

+O g
–
VD/2 VO 100 G = 1k
5 +
–
VD/2 G = 100
+ 80
0 VCM
(Any Gain) 60 G = 10
A3 – Output A3 + Output
–5 Swing Limit
Swing Limit 40 G=1
Lim
it
–10 – O ed by by A 1 g
utpu A ited in 20
t Sw 2
ing Lim put Sw
O ut
–15 – 0
–15 –10 –5 0 5 10 15 10 100 1k 10k 100k 1M
Output Voltage (V) Frequency (Hz)

NEGATIVE POWER SUPPLY REJECTION INPUT- REFERRED NOISE VOLTAGE

vs FREQUENCY vs FREQUENCY
140 1k
Input-Referred Noise Voltage (nV/√ Hz)

120
Power Supply Rejection (dB)

G = 1k
100
100
G = 100
80 G=1
G = 10
60 G = 10
G=1 10
40 G = 100, 1k

20 G = 1k
BW Limit
0 1
10 100 1k 10k 100k 1M 1 10 100 1k 10k
Frequency (Hz) Frequency (Hz)

PGA204/205 6
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

INPUT-REFERRED INPUT BIAS AND INPUT OFFSET CURRENT

OFFSET VOLTAGE WARM-UP vs TIME vs TEMPERATURE
6 2

Input Bias and Input Offset Current (nA)

4
Offset Voltage Change (µV)

G > 100 1
2
±IB
0 0

–2 IOS
–1
–4

–6 –2
0 15 30 45 60 75 90 105 120 –75 –50 –25 0 25 50 75 100 125
Time from Power Supply Turn-on (s) Temperature (°C)

INPUT BIAS CURRENT INPUT BIAS CURRENT

vs DIFFERENTIAL INPUT VOLTAGE vs COMMON-MODE INPUT VOLTAGE
3 3
Both Inputs
2 2 |Ib1| + |Ib2|
Input Bias Current (mA)
One Input
Input Current (mA)

1 1
Over-Voltage
0 0 Protection
Over-Voltage Normal
Protection Operation
–1 G=1 –1

G = 10 One Input
–2 –2

G = 100, 1k Both Inputs

–3 –3
–45 –30 –15 0 15 30 45 –45 –30 –15 0 15 30 45
Differential Overload Voltage (V) Common-Mode Voltage (V)

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY SLEW RATE vs TEMPERATURE

32 1.0

28
0.8
G ≤ 10
Output Voltage (Vp-p)

24
G=8 or 10
Slew Rate (V/µs)

20 0.6
16

12 0.4

8
0.2
4

0 0
10 100 1k 10k 100k 1M –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

7 PGA204/205
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

OUTPUT CURRENT LIMIT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE

30 6.0
Short Circuit Current (mA)

Quiescent Current (mA)

25 5.5

+|ICL|
20 5.0

–|ICL|
15 4.5

10 4.0
–40 –15 10 35 60 85 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

QUIESCENT CURRENT
vs POWER SUPPLY VOLTAGE POSITIVE OUTPUT SWING vs TEMPERATURE
5.2 16
VS = ±15V
V+ 14
Quiescent Current (mA)

5.0 12
Output Voltage (V)

VS = 11.4
10

4.5 8

6
VS = ±4.5
4.0 4
V–
2

3.5 0
0 ±5 ±10 ±15 ±20 –75 –50 –25 0 25 50 75 100 125
Power Supply Voltage (V) Temperature (°C)

NEGATIVE OUTPUT SWING vs TEMPERATURE

–16
VS = ±15V
–14

–12
Output Voltage (V)

VS = 11.4
–10

–8

–6
VS = ±4.5
–4

–2

0
–75 –50 –25 0 25 50 75 100 125
Temperature (°C)

PGA204/205 8
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

SMALL-SIGNAL RESPONSE, G = 1 LARGE-SIGNAL RESPONSE, G = 1

+200mV +10V

–200mV –10V

SMALL-SIGNAL RESPONSE, G = 10 LARGE-SIGNAL RESPONSE, G = 10

+200mV
+10V

–200mV –10V

SMALL-SIGNAL RESPONSE, G = 1000 LARGE-SIGNAL RESPONSE, G = 1000

+200mV +10V

–200mV –10V

9 PGA204/205
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, and VS = ±15V, unless otherwise noted.

INPUT-REFERRED NOISE,
0.1 TO 10Hz, G = 1000 NOISE, 0.1 TO 10Hz, G = 1

0.2µV/Div 0.5µV/Div

1s/Div 1s/Div

APPLICATION INFORMATION be used to sense the output voltage directly at the load for
best accuracy.
Figure 1 shows the basic connections required for operation
of the PGA204/205. Applications with noisy or high imped-
DIGITAL INPUTS
ance power supplies may require decoupling capacitors
close to the device pins as shown. The digital inputs A0 and A1 select the gain according to the
The output is referred to the output reference (Ref) terminal logic table in Figure 1. Logic “1” is defined as a voltage
which is normally grounded. This must be a low-impedance greater than 2V above digital ground potential (pin 14).
connection to assure good common-mode rejection. A resis- Digital ground can be connected to any potential from the
tance of 5Ω in series with the Ref pin will cause a typical V– power supply to 4V less than V+. Digital ground is
device to degrade to approximately 80dB CMR (G=1). normally connected to ground. The digital inputs interface
directly CMOS and TTL logic components.
The PGA204/205 has an output feedback connection (pin
12). Pin 12 must be connected to the output terminal (pin 11) Approximately 1µA flows out of the digital input pins when
for proper operation. The output Feedback connection can a logic “0” is applied. Logic input current is nearly zero with
a logic “1” input. A constant current of approximately

+15V
1µF

VO1
1
PGA204
– 4 Over-Voltage
VIN PGA205
Protection Feedback
A1
12
25kΩ 25kΩ

16
Digitally Selected
15 A3 VO
Feedback Network 11
14
+ –
VO = G (VIN – VIN )

Ref
A2
+ 5 Over-Voltage 10
VIN 25kΩ 25kΩ
Protection

6 7 9 8
1µF Sometimes shown in simplified form:
VOS VO2
GAIN Adj –
VIN
PGA204 PGA205 A 1 A0
PGA204 VO
1 1 0 0 +15V +
VIN
10 2 0 1
100 4 1 0
1000 8 1 1 A1 A0

FIGURE 1. Basic Connections.

®

PGA204/205 10
 Some applications select gain of the PGA204/205 with
V+
4 Over-Voltage switches or jumpers. Figure 2 shows pull-up resistors con-
– Protection nected to assure a noise-free logic “1” when the switch,
VIN A1
jumper or open-collector logic is open or off. Fixed-gain
applications can connect the logic inputs directly to V+ or
100kΩ 100kΩ
16 V– (or other valid logic level); no resistor is required.
Digitally Selected
15 Feedback Network
14 OFFSET VOLTAGE
Voltage offset of the PGA204/205 consists of two compo-
+ nents—input stage offset and output stage offset. Both
VIN A2
Over-Voltage
Protection
components are specified in the specification table in equa-
Switches, jumpers 5
tion form:
or open-collector 6 7 9
logic output. Digital ground can VOS = VOSI + VOSO / G (1)
alternatively be connected VOS VO2
to V– power supply. Adj where:
VOS total is the combined offset, referred to the input.
FIGURE 2. Switch or Jumper-Selected Digital Inputs.
VOSI is the offset voltage of the input stage, A1 and A2.
1.3mA flows in the digital ground pin. It is good practice to VOSO is the offset voltage of the output difference
return digital ground through a separate connection path so amplifier, A3.
that analog ground is not affected by the digital ground VOSI and VOSO do not change with gain. The composite
current. offset voltage VOS changes with gain because of the gain
The digital inputs, A0 and A1, are not latched; a change in term in equation 1. Input stage offset dominates in high gain
logic inputs immediately selects a new gain. Switching time (G≥100); both sources of offset may contribute at low gain
of the logic is approximately 1µs. The time to respond to (G=1 to 10).
gain change is effectively the time it takes the amplifier to
settle to a new output voltage in the newly selected gain (see OFFSET TRIMMING
settling time specifications). Both the input and output stages are laser trimmed for very
Many applications use an external logic latch to access gain low offset voltage and drift. Many applications require no
control data from a high speed data bus (see Figure 7). Using external offset adjustment.
an external latch isolates the high speed digital bus from Figure 3 shows an optional input offset voltage trim circuit.
sensitive analog circuitry. Locate the latch circuitry as far as
This circuit should be used to adjust only the input stage
practical from analog circuitry.
offset voltage of the PGA204/205. Do this by programming

VO1 V+
1 13
PGA204
– 4 Over-Voltage
VIN PGA205
Protection Feedback
A1
12
25kΩ 25kΩ
Resistors can be substituted
for REF200. Power supply
16 rejection will be degraded.
A1 Digitally Selected
15 A3
A0 Feedback Network 11 +
VO = G (VIN –
– VIN ) + VREF V+
14
Digital
Ground
VREF 100µA
A2 1/2 REF200
+ 5 Over-Voltage 10
VIN 25kΩ 25kΩ
Protection
OPA177 100Ω
6 7 9 8
±10mV 10kΩ
VO2 V– Adjustment Range 100Ω
Input Offset 200kΩ Output Offset
Adjustment to 1MΩ Adjustment 100µA
Trim Range
V+ 1/2 REF200
≈ ±250µV

V–

FIGURE 3. Optional Offset Voltage Trim Circuit.

®

11 PGA204/205
it to its highest gain and trimming the output voltage to zero
with the inputs grounded. Drift performance usually im-
proves slightly when the input offset is nulled with this Microphone,
procedure. Hydrophone PGA204
etc.
Do not use the input offset adjustment to trim system offset
or offset produced by a sensor. Nulling offset that is not 47kΩ 47kΩ
produced by the input amplifiers will increase temperature
drift by approximately 3.3µV/°C per 1mV of offset adjust-
ment.
Many applications that need input stage offset adjustment do
not need output stage offset adjustment. Figure 3 also shows
Thermocouple PGA204
a circuit for adjusting output offset voltage. First, adjust the
input offset voltage as discussed above. Then program the
device for G=1 and adjust the output to zero. Because of the
interaction of these two adjustments at G=8, the PGA205 10kΩ
may require iterative adjustment.
The output offset adjustment can be used to trim sensor or
system offsets without affecting drift. The voltage applied to
the Ref terminal is summed with the output signal. Low PGA204
impedance must be maintained at this node to assure good
common-mode rejection. This is achieved by buffering the
trim voltage with an op amp as shown. VR Center-tap provides
bias current return.
NOISE PERFORMANCE
The PGA204/205 provides very low noise in most applica- Bridge
tions. Low frequency noise is approximately 0.4µVp-p mea-
sured from 0.1 to 10Hz. This is approximately one-tenth the PGA204
noise of “low noise” chopper-stabilized amplifiers.

Bias current return

INPUT BIAS CURRENT RETURN PATH inherrently provided by source.
The input impedance of the PGA204/205 is extremely high—
approximately 1010Ω. However, a path must be provided for FIGURE 4. Providing an Input Common-Mode Current
the input bias current of both inputs. This input bias current Path.
is typically less than ±1nA (it can be either polarity due to
cancellation circuitry). High input impedance means that INPUT COMMON-MODE RANGE
this input bias current changes very little with varying input
The linear common-mode range of the input op amps of the
voltage.
PGA204/205 is approximately ±12.7V (or 2.3V from the
Input circuitry must provide a path for this input bias current power supplies). As the output voltage increases, however,
if the PGA204/205 is to operate properly. Figure 4 shows the linear input range will be limited by the output voltage
provisions for an input bias current path. Without a bias swing of the input amplifiers, A1 and A2. The common-
current return path, the inputs will float to a potential which mode range is related to the output voltage of the complete
exceeds the common-mode range of the PGA204/205 and amplifier—see performance curve “Input Common-Mode
the input amplifiers will saturate. If the differential source Range vs Output Voltage”.
resistance is low, bias current return path can be connected
A combination of common-mode and differential input
to one input (see thermocouple example in Figure 4). With
voltage can cause the output of A1 or A2 to saturate. Figure
higher source impedance, using two resistors provides a
5 shows the output voltage swing of A1 and A2 expressed in
balanced input with possible advantages of lower input
terms of a common-mode and differential input voltages.
offset voltage due bias current and better common-mode
Output swing capability of these internal amplifiers is the
rejection.
same as the output amplifier, A3. For applications where
Many sources or sensors inherently provide a path for input input common-mode range must be maximized, limit the
bias current (e.g. the bridge sensor shown in Figure 4). output voltage swing by selecting a lower gain of the
These applications do not require additional resistor(s) for PGA204/205 (see performance curve “Input Common-Mode
proper operation. Voltage Range vs Output Voltage”). If necessary, add gain
after the PGA204/205 to increase the voltage swing.

PGA204/205 12
 G • VD VO1 V+
VCM –
2 1 13
PGA204
4 Over-Voltage PGA205
Protection Feedback
A1
12
25kΩ 25kΩ
VD
2
16
A1 Digitally Selected
15 A3 VO
A0 Feedback Network 11
14
Digital
VD Ground
2
A2 Ref
VCM 5 Over-Voltage 10
25kΩ 25kΩ
Protection

9 8
G • VD
VCM +
2 VO2 V–

FIGURE 5. Voltage Swing of A1 and A2.

Input-overload often produces an output voltage that appears

V+
normal. For example, consider an input voltage of +20V on
one input and +40V on the other input will obviously exceed
the linear common-mode range of both input amplifiers.
Since both input amplifiers are saturated to the nearly the
same output voltage limit, the difference voltage measured 47kΩ 47kΩ
by the output amplifier will be near zero. The output of the
PGA204/205 will be near 0V even though both inputs are –
VIN
overloaded.
A1 PGA204
A0 PGA205
+
INPUT PROTECTION VIN

The inputs of the PGA204/205 are individually protected for B C

voltages up to ±40V. For example, a condition of –40V on A D
X

one input and +40V on the other input will not cause
damage. Internal circuitry on each input provides low series
impedance under normal signal conditions. To provide D1, D2: IN4148, IN914, etc.
equivalent protection, series input resistors would contribute
excessive noise. If the input is overloaded, the protection
circuitry limits the input current to a safe value (approxi- SWITCH GAIN
mately 1.5mA). The typical performance curve “Input Bias POSITION PGA204 PGA205
Current vs Common-Mode Input Voltage” shows this input A 1 1
current limit behavior. The inputs are protected even if no B 10 2
power supply voltage is present. C 100 4
D 1000 8

FIGURE 6. Switch-Selected PGIA.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

13 PGA204/205
 +15V

14 2 VO1 V+
1 13
HI-509
4 PGA204
4 Over-Voltage PGA205
5 Protection Feedback
8 A1
– 12
VIN 25kΩ 25kΩ
6

7 A1 16
Digitally Selected
A0 15 A3 VO
13 Feedback Network 11
14
12
9
+
VIN
A2 Ref
11 5 Over-Voltage 10
25kΩ 25kΩ
Protection
10

A0 A1 6 7 9 8

3 15 1 16 VOS VO2 V–
Adj
–15V

Data Out
To Address
74HC574 CK
Decoding Logic
Data In

Data Bus

FIGURE 7. Multiplexed-Input Programmable Gain IA.

A0 A1

VO1
–
VIN PGA204
+ VO
VIN PGA205
Ref
VO2

220Ω A1 A0 20kΩ 20kΩ

OPA177

FIGURE 8. Shield Drive Circuit.

+
VIN
A1 A1
AO PGA205 AO PGA205 VO –
VO
– VIN PGA204
VIN PGA205
+
Ref R1
C1
1MΩ
0.1µF
A1 A0

GAIN A3 A2 A1 A0
1 0 0 0 0 1
f–3dB =
2 0 1 0 0 OPA602 2πR1C1
4 1 0 0 0 = 1.59Hz
8 1 1 0 0
16 1 1 0 1
32 1 1 1 0
64 1 1 1 1

FIGURE 9. Binary Gain Steps, G=1 to G=64. FIGURE 10. AC-Coupled PGIA.
®

PGA204/205 14
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

PGA204AP ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type PGA204AP
& no Sb/Br)
PGA204AU ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
& no Sb/Br)
PGA204AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
& no Sb/Br)
PGA204AU/1KE4 ACTIVE SOIC DW 16 1000 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
& no Sb/Br)
PGA204AUE4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
& no Sb/Br)
PGA204AUG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
& no Sb/Br)
PGA204BP ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type PGA204BP
& no Sb/Br)
PGA204BPG4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type PGA204BP
& no Sb/Br)
PGA204BU ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR PGA204BU
& no Sb/Br)
PGA204BU/1K ACTIVE SOIC DW 16 1000 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR PGA204BU
& no Sb/Br)
PGA205AP ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 PGA205AP
& no Sb/Br)
PGA205AU ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205AU
& no Sb/Br)
PGA205AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205AU
& no Sb/Br)
PGA205AUG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205AU
& no Sb/Br)
PGA205BP ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 PGA205BP
& no Sb/Br)
PGA205BU ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205BU
& no Sb/Br)
PGA205BUG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205BU
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PGA204AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PGA204BU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PGA205AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PGA204AU/1K SOIC DW 16 1000 367.0 367.0 38.0
PGA204BU/1K SOIC DW 16 1000 367.0 367.0 38.0
PGA205AU/1K SOIC DW 16 1000 367.0 367.0 38.0

Pack Materials-Page 2
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