AN150

Application Note
CS5531/32/33/34 FREQUENTLY ASKED QUESTIONS
INTRODUCTION A software reset is performed by writing a “1” to
The CS5531/32/33/34 are 16 and 24-bit ADCs that the RS bit (Bit 29) in the Configuration Register.
include an ultra low-noise amplifier, a 2 or 4-chan- When a reset is complete, the RV bit (Bit 28) in the
nel multiplexer, and various conversion and cali- Configuration Register will be set to a “1” by the
bration options. This application note is intended to ADC. Any other bits in the Configuration Register
provide a resource to help users understand how to that need to be changed must be done with a sepa-
best use the features of these ADCs. The “Getting rate write to the register after the software reset is
Started” section outlines the order in which certain performed.
things should be done in software to ensure that the Set Up the Configuration Register
converter functions correctly. The “Questions and
Answers” section discusses many of the common After a software reset has been performed, the Con-
questions that arise when using these ADCs for the figuration Register can be written to configure the
first time. general operation parameters of the device. This
step can be omitted if the system is using the de-
GETTING STARTED fault register value. Particular attention must be
paid to the setting of the VRS bit (Bit 25). The VRS
Initialize the ADCs Serial Port
bit should be set to “1” if the voltage on the VREF+
The CS5531/32/33/34 do not have a reset pin. A re- and VREF- pins is 2.5 V or less. If the voltage on
set is performed in software by re-synchronizing the VREF+ and VREF- pins is greater than 2.5V,
the serial port and doing a software reset. Re-syn- the VRS bit should be set to “0”.
chronizing the serial port ensures that the device is
expecting a valid command. It does not initiate a Set up the Channel Setup Registers
reset of the ADC, and all of the register settings of The Channel Setup Registers determine how the
the device are retained. part should operate when given a conversion or cal-
A serial port re-synchronization is performed by ibration command. If the system is using the device
sending 15 (or more) bytes of 0xFF (hexadecimal) with its default settings, the Channel Setup Regis-
to the converter, followed by a single byte of 0xFE. ters need not be written. Whether the Channel Set-
Note that anytime a command or any other infor- up Registers are written or not, they should be
mation is to be sent to or read from the ADC’s se- configured for the desired operation of the device
rial port, the CS pin must be low. before performing any calibrations or conversions.

Perform a Software Reset Calibrate the ADC

After re-synchronizing the ADCs serial port, a soft- The CS5531/32/33/34 can be calibrated using the
ware reset should be performed on the device. A re- on-chip calibration features for more accuracy. The
set will set all of the internal registers to their parts do not need to be calibrated to function, and
default values, as detailed in the datasheet. in some systems a calibration step may not be nec-

Cirrus Logic, Inc.

Crystal Semiconductor Products Division Copyright  Cirrus Logic, Inc. 2001 SEP ‘01
P.O. Box 17847, Austin, Texas 78760 (All Rights Reserved) AN150REV2
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com 1
 AN150

essary. Any offset or gain errors in the ADC itself 2, and when the bit is set to ‘1’, A = 1. RG is the
and the front-end analog circuitry will remain if the decimal value of the digital gain register, which is
device is left uncalibrated. discussed in a later section. For the purposes of this
If the built-in calibration functions of the device are section, the value of RG is 1.0.
to be used, the calibrations should be performed be- The input voltage span in unipolar mode will be
fore any conversions take place. Calibrations are from 0 V to the positive full-scale input voltage
performed by sending the appropriate calibration computed using Equation 1. In bipolar mode, the
command to the converter’s serial port, and waiting input voltage span is twice as large, since the input
until the SDO line falls low, which indicates that range goes from negative full-scale (-VFS) to posi-
the calibration has completed. New commands tive full-scale (VFS). So for unipolar mode, the in-
should not be sent to the converter until the calibra- put voltage span is VFS, and in bipolar mode, it is 2
tion cycle is complete. More detail about perform- * VFS.
ing calibrations can be found later in this document Example: Using a 5V voltage reference, with the
and in the datasheet. VRS bit set to 0 in the 32X bipolar gain range, we
Perform Conversions see that (VREF+)-(VREF-) = 5 V, G = 32, and A =
2. Using Equation 1, V FS = (5 V)/(32 * 2) = 78.125
Conversions can be performed by sending the ap- mV. Since we are using bipolar mode, the input
propriate command to the converter, waiting for voltage span becomes 2 * VFS = 156.25 mV, or
SDO to fall, and then clocking the data from the se- ±78.125 mV.
rial port. New commands should not be sent to the
converter during a conversion cycle. The various How are the digital output codes mapped to
conversion modes and options are discussed in the analog input voltage of the converters?
more detail later in this document and in the The output codes from the converter are mapped as
datasheet. either straight binary or two’s complement binary
QUESTIONS AND ANSWERS values, depending on whether the part is in unipolar
or bipolar mode. The part measures voltage on the
How is the input voltage span of the con- analog inputs as the differential between the AIN+
verter calculated? and AIN- pins (AIN+ - AIN-). The smallest amount
The positive full-scale input voltage (VFS) is deter- of voltage change on the analog inputs which will
mined by Equation 1. cause a change in the output code from the convert-
( ( VREF+ ) – ( VREF- ) ) 1
er is known as an “LSB” (Least Significant Bit),
V FS = -------------------------------------------------------- × -------
(G × A) RG because it is the LSB of the converter’s output
word that is affected by this voltage change. The
Equation 1. Full-Scale Input Voltage
size of one LSB can be calculated with Equation 2.
In Equation 1, (VREF+) - (VREF-) is the differ- ( V SPAN )
ence between the voltage levels on the VREF+ and LSB = ---------------------
( 2N )
VREF- pins of the converter. The variable G in the
Equation 2. LSB Size
equation represents the setting of the programma-
ble-gain instrumentation amplifier (PGIA) inside
the part. The variable A in the equation is depen- In Equation 2, “VSPAN” is the full input voltage
dent on the setting of the VRS bit in the Configura- range as determined by the voltage reference,
tion register (bit 25). When this bit is set to ‘0’, A = PGIA setting, and gain register value. “N” is the

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CS5531/33 16-Bit Output Coding CS5532/34 24-Bit Output Coding

Unipolar Input Offset Bipolar Input Two's Unipolar Input Offset Bipolar Input Two's
Voltage Binary Voltage Complement Voltage Binary Voltage Complement
>(VFS-1.5 LSB) FFFF >(VFS-1.5 LSB) 7FFF >(VFS-1.5 LSB) FFFFFF >(VFS-1.5 LSB) 7FFFFF
VFS-1.5 LSB FFFF 7FFF VFS-1.5 LSB FFFFFF 7FFFFF
------ VFS-1.5 LSB ------ ------ VFS-1.5 LSB ------
FFFE 7FFE FFFFFE 7FFFFE
VFS/2-0.5 LSB 8000 0000 VFS/2-0.5 LSB 800000 000000
------ -0.5 LSB ------ ------ -0.5 LSB ------
7FFF FFFF 7FFFFF FFFFFF
+0.5 LSB 0001 8001 +0.5 LSB 000001 800001
------ -VFS+0.5 LSB ------ ------ -VFS+0.5 LSB ------
0000 8000 000000 800000
<(+0.5 LSB) 0000 <(-VFS+0.5 LSB) 8000 <(+0.5 LSB) 000000 <(-VFS+0.5 LSB) 800000

Table 1: Output Coding for 16-bit CS5531/33 and 24-bit CS5532/34.

number of bits in the output word (16 for the In bipolar mode, half of the available codes are
CS5531/33 and 24 for CS5532/34). used for positive inputs, and the other half are used
Example: Using the CS5532 in the 64X unipolar for negative inputs. The input voltage is represent-
range with a 2.5V reference and the gain register ed by a two’s complement number. When the dif-
set to 1.0, VSPAN is nominally 39.0625 mV, and N ferential input voltage is equal to 0 V ±1/2 LSB, the
is 24. The size of one LSB is then equal to 39.0625 output code from the converter will equal zero. As
mV / 2^24, or approximately 2.328 nV. in unipolar mode, when the differential voltage ex-
ceeds +1/2 LSB, the converter will output binary
The output coding for both the 16-bit and 24-bit values related to the magnitude of the voltage in-
parts depends on whether the device is used in uni- put. When the input voltage is within 1/2 LSB of
polar or bipolar mode, as shown in Table 1. In uni- the maximum input level however, the code from
polar mode, when the differential input voltage is the converter will be a single 0 followed by all 1’s
zero Volts ±1/2 LSB, the output code from the con- (hexadecimal 7FFF for the CS5531/33 and hexa-
verter will be zero. When the differential input decimal 7FFFFF for the CS5532/34). For negative
voltage exceeds +1/2 LSB, the converter will out- differential inputs, the MSB of the output word will
put binary code values related to the magnitude of be set to 1. When the differential input voltage is
the input voltage (if the differential input voltage is within 1/2 LSB of the full-scale negative input volt-
equal to 434 LSBs, then the output of the converter age, the code from the converter will be a single 1
will be 434 decimal). When the input voltage is followed by all 0’s (hexadecimal 8000 for the
within 1/2 LSB of the maximum input level, the CS5531/33 and hexadecimal 800000 for the
codes from the converter will max out at all 1’s CS5532/34). As the negative differential voltage
(hexadecimal FFFF for the CS5531/33 and hexa- gets closer to zero, the output codes will count up-
decimal FFFFFF for the CS5532/34). If the differ- wards until the input voltage is between -1 1/2 and
ential input voltage is negative (AIN+ is less than -1/2 LSB, when the output code will be all 1’s
AIN-), then the output code from the converter will (hexadecimal FFFF for the CS5531/33 and hexa-
be equal to zero, and the overflow flag will be set. decimal FFFFFF for the CS5532/34).
If the differential input voltage exceeds the maxi-
mum input level, then the code from the converter To calculate the expected decimal output code that
will be equal to all 1’s, and the overflow flag will you would receive from the ADC for a given input
be set. voltage, divide the given input voltage by the size

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of one LSB. For a 5 mV input signal when the LSB system can be enhanced by selecting the appropri-
size is 4 nV, the expected output code (decimal) ate reference range.
from the converter would be 1,250,000. In a system that is performing ratiometric measure-
What is the relationship of the VREF input ments, using a 5 V reference is usually the best op-
voltage and the VRS bit to the analog inputs tion. Ratiometric bridge sensors typically have a
of the converter? very low output voltage range that scales directly
with the excitation voltage to the sensor. Because
The voltage present on the VREF+ and VREF- in- the converter’s input span can be the same with ei-
puts have a direct relationship to the input voltage ther a 2.5 V reference or a 5 V reference, and the
span of the converter. The differential voltage be- voltage output from the ratiometric sensor will be
tween the VREF inputs ((VREF+) - (VREF-)) twice as large with a 5 V excitation, the system can
scales the span of the analog input proportionally. achieve higher signal to noise performance when
If the VREF voltage changes by 5%, the analog in- the sensor excitation and the voltage reference are
put span will also change by 5%. The VREF input at 5 V.
voltage does not limit the absolute magnitude of the
voltages on the analog inputs, but only sets the For systems in which absolute voltage accuracy is
slope of the transfer function (codes output vs. volt- a concern, using a 2.5 V reference has some advan-
age input) of the converter. The analog input volt- tages. There are a wide variety of precision 2.5 V
ages are only limited with respect to the supply reference sources available which can be powered
voltages (VA+ and VA-) on the part. See the from the same 5 V source as the ADC. However,
“Common-mode + signal on AIN+ or AIN-” dis- most precision 5 V references require more than 5
cussion in this document for more details on these V on their power supplies, and a second supply
limitations. would be needed to provide the operating voltage
to a voltage reference. Since the same input ranges
The VRS bit in the configuration register also has a are available with either reference voltage, a 2.5 V
direct effect on the analog input span of the con- reference provides a more cost and space-effective
verter. When the differential voltage on the VREF solution. Additionally, for systems where the 1X
pins is between 1 V and 2.5 V, the VRS bit should gain range is used, a 2.5 V reference voltage gives
be set to ‘1’. When this voltage is greater than 2.5 the user the option of using the self gain calibration
V, the VRS bit should be set to ‘0’. When set to ‘0’, function of the ADC, where a 5 V reference does
a different capacitor is used to sample the VREF not.
voltage, and the input span of the converter is
halved. The proper setting of this bit is crucial to What are the noise contributions from the
the optimal operation of the converter. If this bit is amplifier and the modulator?
set incorrectly, the converter will not meet the data The amplifier used in the 2X-64X gain ranges of
sheet noise specifications. the part has typical input-referred noise of 6
The purpose of the VRS bit is to optimize the per- nV/√Hz for the -BS versions, and 12 nV/√Hz for
formance for two different types of systems. In the -AS versions. The modulator has typical noise
some systems, a precision 2.5 V reference is used of 70 nV/√Hz for the -BS versions, and 110
to get absolute accuracy of voltage measurement. nV/√Hz for the -AS versions at word rates of 120
Other systems use a 5 V source to provide both the samples/s and less. At word rates higher than 120
reference voltage and an excitation voltage for a ra- samples/s, the modulator noise begins to rise, and
tiometric bridge sensor. The performance of the is difficult to model with an equation. The

4 AN150REV2
 AN150

CS5531/32/33/34 datasheet lists the typical RMS analog inputs?

noise values for all combinations of gain range and In the 1X gain range, the inputs are buffered with a
word rate. rough-fine charge scheme. With this input struc-
In the 32X and 64X gain ranges, the amplifier noise ture, the modulator sampling capacitor is charged
dominates, and the modulator noise is not very sig- in two phases. During the first (rough) phase, the
nificant. As the gain setting decreases, the amplifi- capacitor is charged to approximately the correct
er noise becomes less significant, and the value using the 1X buffer amplifier, and the neces-
modulator becomes the dominant noise source in sary current is provided by the buffer output to the
the 1X and 2X gain ranges. The noise density from sampling capacitor. During the second (fine) phase,
the amplifier and the modulator for word rates of the capacitor is connected directly to the input, and
120 samples/s and lower can be calculated using the necessary current to charge the capacitor to the
Equation 3. final value comes from the AIN+ and AIN- lines.
The size of the sampling capacitor, the offset volt-
2 2
( NA × G ) + ( NM ) age of the buffer amplifier, and the frequency at
Noise Density = ----------------------------------------------------
G
which the front-end switches are operating can be
Equation 3. Noise Density multiplied together (CxVxF) to calculate the input
current. The buffer amplifier’s offset voltage and
In Equation 3, G refers to the gain setting of the the modulator sampling capacitor size are a func-
PGIA. NA refers to the amplifier noise, and NM re- tion of the silicon manufacturing process, and can-
fers to the modulator noise. By using the noise not be changed. The frequency at which the
numbers at the beginning of this section, a noise switches are operating is determined directly by the
density number can be found for any gain range master clock for the part, and is the only variable
setting. The typical RMS noise for a given word that users can modify which will have an effect on
rate can be estimated by multiplying the noise den- the input current in this mode. The input current
sity at the desired gain range by the square root of specified in the datasheet assumes a 4.9152 MHz
the filter’s corner frequency for that word rate. This master clock.
estimate does not include the noise that is outside In the 2X-64X gain ranges, the input current is due
the filter bandwidth, but it can give a rough idea of to small differences in the silicon that makes up the
what the typical noise would be for those settings. chopping switches on the front end of the amplifier.
The true RMS noise number will be slightly higher, The difference between these switches produces a
as indicated by the RMS noise tables in the small charge injection current on the analog inputs.
datasheet. The frequency at which the switches are operating
The apparent noise numbers seen at the output of is derived directly from the master clock of the part,
the converter will be affected by the setting of the and the input current will change as the master
internal gain register of the part. The typical RMS clock frequency changes. Higher master clock fre-
noise numbers calculated in this section and shown quencies will produce higher input currents. Like-
in the datasheet’s RMS noise tables correspond to wise, changes in the VA+ and VA- supply voltages
the noise seen at the converter’s output using a gain will change the amount of charge injection that is
register setting of approximately 1.0. produced by the switches, and higher supply volt-
ages will produce more current on the inputs. The
What factors affect the input current on the input current specified in the datasheet assumes a
4.9152 MHz master clock and 5 V between the

AN150REV2 5
 AN150

VA+ and VA- supply pins. 0x00000000, the measured output code from the
converter with a given input voltage is 0x000100
What factors affect the input current on the (256 decimal). When the offset register is set to
voltage reference inputs? 0x00001E00 (30 decimal, after truncating the last
The input structure on the VREF pins is similar to byte), the expected shift in output code from the
the input structure for the 1X gain range. The inputs converter would be 1.83007966 * 0x00001E =
are buffered with a rough-fine charge scheme. 0x000036 (54 decimal). Subtracting this from the
However, the size of the capacitor (C) in the equa- original output code gives 0x000100 - 0x000036 =
tion CxVxF changes with the setting of the VRS bit 0x0000CA (202 decimal).
in the configuration register. With the VRS bit set The contents of the gain registers are 30-bit fixed-
to ‘1’, the capacitor size is cut in half, which also point numbers which can range from 0 to 64 - 2-24
reduces the VREF input current by 1/2. Like the an- when expressed as decimal numbers (with two
alog input current, the VREF input current will leading 0’s to extend the register length to 32 bits).
change with clock frequency, and is specified with Although the maximum gain register setting is
a 4.9152 MHz clock. nearly 64, gain register settings above 40 should
How do the offset and gain register settings not be used. The gain register has a scaling effect
affect the input range of the converter? on the output codes of the converter. After subtract-
ing the contents of the offset register, every conver-
The offset and gain registers have a direct effect on sion is multiplied by the gain register for that
the output codes of the converter. Because of their particular channel. This changes the slope of the
effects on the output codes from the converter, they converter, and has an inverse proportional relation-
also have an apparent effect on the input voltage ship to the input span of the converter, as seen in
span of the converter. Equation 1, where the decimal equivalent of the
The contents of the offset registers are 24-bit 2’s gain register is represented with the variable RG.
complement numbers (with a trailing byte of 0’s to Example: With a gain register setting of
extend the register length to 32 bits) that shift the 0x01000000 (1.0 decimal) and a given input volt-
output codes from the converter up or down by a age, the output code from the converter is
certain amount. The value in the offset register for 0x009C40 (40,000 decimal). If the gain register is
a given channel times a scaling value of changed to 0x01C00000 (1.75 decimal), the output
1.83007966 will be subtracted from every conver- code from the converter becomes 0x009C40 * 1.75
sion on that channel before it is output from the = 0x011170 (70,000 decimal). Thus, the effective
converter. Because this shifts the output of the con- input range has also been scaled by 1/1.75.
verter, it will also shift the input span up or down,
depending on the contents of the offset register. Because this multiplication is done after the sub-
The corresponding effect on the input voltage de- traction of the offset register, the gain register set-
pends on both the input span of the converter, and ting has a direct effect on the offset introduced by
the gain register setting. The multiplication factor the offset register as well. It is for this reason that
of 1.83007966 is compensation for the effects of any adjustments to the offset register should take
the digital filter on this register. The offset register into account the gain register value, as well as the
may be used to remove a large bridge offset, or oth- 1.83007966X filter gain factor that will be applied
er offset errors in a system. afterwards.

Example: With an offset register setting of What is the purpose of the Filter Rate Select

6 AN150REV2
 AN150

(FRS) bit in the configuration register? delay time. These registers must be modified when
the part is to be operated in a mode other than the
The FRS bit (bit 19 in the Configuration Register)
default settings. An entire channel setup register
is used to select between two different sets of out-
(two Setups) must be read or written all at once,
put word rates. When running the ADC from a
even if one of the Setups in the register is not being
4.9152 MHz clock, the FRS bit can be toggled with
modified. If a “write all” or “read all” command is
a simple software switch to provide either 50 Hz or
issued on the channel setup registers, all four of the
60 Hz rejection in situations where this is applica-
registers (eight Setups) must be written or read.
ble. The default state of the FRS bit is zero. In this
mode, the word rates from the ADC are 7.5, 15, 30, When issuing a conversion or calibration command
60, 120, 240, 480, 960, 1920, and 3840 samples/s to the converter, the channel setup register pointer
(when running from a 4.9152 MHz clock). When (CSRP) bits indicate which Setup to follow when
the FRS bit is set to one, these word rates and their performing the calibration or conversion. The con-
corresponding filter characteristics scale by a factor verter will configure itself according to the infor-
of 5/6, producing output word rates of 6.25, 12.5, mation found in the indicated Setup, and perform
25, 50, 100, 200, 400, 800, 1600, and 3200 sam- the desired operation. The Setups allow the user to
ples/s. All of the word rates and filter characteris- select from multiple converter settings without
tics in the part will also scale with the master clock having to re-configure the converter each time the
frequency. Setting the FRS bit in the configuration configuration (channel, gain setting, word rate,
register has the same effect as changing the clock etc.) needs to change.
frequency by a factor of 5/6, without having to
How is the delay time (DT) bit in each Setup
change the hardware on the board.
used?
How are the channel setup registers in the The delay time (DT) bit in each Setup register adds
converters used? a fixed amount of delay between the new state of
The channel setup registers each hold two 16-bit the output latch pins, and the start of a new conver-
“Setups”, which can be thought of as pre-defined sion cycle. This allows the user to control circuitry
calibration and conversion instructions. These 16- on the front-end of the device with slower response
bit register spaces contain all of the information times or power-on times with the output latch bits
needed by the converter to perform a conversion or of the converter, and start the conversion after the
calibration in the desired operating mode. The bit front-end circuitry has settled. The delay time is
selections in the Setups allow the user to choose the fixed at 1280 master clock cycles (approximately
physical channel, gain range, polarity, and word 260 µs when running from a 4.9152 MHz clock)
rate to convert with, as well as the desired state of when the FRS bit in the configuration register is set
the two output latch pins. They also define whether to ‘0’. When the FRS bit is set to ‘1’, the delay time
the current source used for detection of an open cir- is extended to 1536 clock cycles (approximately
cuit should be turned on, and if a delay should be 312 µs when running from a 4.9152 MHz clock).
added between the switching of the latch outputs For circuitry that takes longer than this to power on
and the beginning of a conversion cycle. By de- or switch, a “dummy” conversion at a different
fault, all of these registers are initially set to convert word rate can be used to add some delay time, or
on channel 1 in the 1X, bipolar input range at an the latch bits can be controlled from the Configura-
output word rate of 120 samples/s with the latch tion Register.
pins both set to ‘0’, the current source off, and no

AN150REV2 7
 AN150

What is the difference between a “self” cali- How accurate is the converter without cali-
bration and a “system” calibration? bration?
A self calibration uses voltages that are available to The converter’s gain settings are not factory
the converter to perform calibrations, and does not trimmed, so if the converter is not calibrated, the
take into account any system-level effects. The absolute gain accuracy is typically ±1%. The track-
converter performs a self offset calibration by dis- ing error between the different PGIA gain settings
connecting the AIN+ and AIN- inputs of the speci- (2X - 64X) is typically about ±0.3%. If absolute ac-
fied channel, and shorting them to the common- curacy is required, the converter should be calibrat-
mode internal to the ADC. The converter then does ed for both offset and gain in the specific ranges
a conversion and computes a value for the offset where it is needed.
register. A self gain calibration is performed by dis-
connecting the AIN+ and AIN- inputs and connect-
What are the advantages of using the on-chip
ing them to the VREF+ and VREF- inputs calibration registers?
respectively. The converter then performs a con- The on-chip calibration registers allow the convert-
version and calculates the gain register value from er to be easily interfaced to a simple, low-cost, 8-bit
that conversion. Self calibrations are only valid in microcontroller without a lot of software overhead.
the 1X gain range with a voltage reference of 1 to The subtraction operation used by the offset regis-
2.5 V. A self calibration of offset is possible in the ter and the multiplication operation used by the
other gain ranges by using the Input Short (IS) bit gain register can both be performed inside the con-
in the Configuration Register. This bit can be set to verter for fast, precise results when using even a
‘1’, and a system offset calibration can be per- very simple microcontroller. The internal registers
formed on the appropriate channel. The IS bit must also provide the user an easy means to use a variety
be set back to ‘0’ for normal operation of the con- of different calibration techniques for more accura-
verter. cy.
System calibrations rely on the correct voltage lev- Why is there no offset DAC in these convert-
els being applied to the voltage inputs during the ers?
calibration operation. For a system offset calibra-
tion, the desired “zero” point should be applied to The high dynamic range of the CS553x family of
the AIN+ and AIN- inputs before the calibration ADCs eliminates the need for an offset DAC. The
command is sent and throughout the calibration offset register can perform the same function that
process. Typically, this point is zero volts, but the an offset DAC would normally do in other ADCs.
converters can calibrate out ±100% of the nominal For example, a typical 2 mV/V bridge has a maxi-
input range in bipolar mode, and ±90% of the nom- mum output of 10 mV with a 5 V excitation supply.
inal input range in unipolar mode. During a system Using the 64X gain range in unipolar mode, there
gain calibration, the desired full-scale signal should is still approximately 29 mV of headroom that can
be applied to the voltage inputs of the converter. accommodate sensor or system offsets. Performing
The CS5531/32/33/34 can calibrate the gain slope a system-level calibration or employing gain scal-
with input voltages that are anywhere between 3% ing techniques allow the user to adjust the input
and 110% of the nominal full-scale voltage. range of the converter to a 0 to 10 mV range after
removing any offset that is present. Using the 7.5
samples/s word rate, the dynamic range of these
converters allows them to still achieve 17 bits of

8 AN150REV2
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noise-free resolution (for the -BS versions of the be performed with more precise equipment, and
parts) over this input range, even in the presence of user error is not a problem. Field calibration has ad-
large offset voltages. vantages also, since it can take into account the ac-
tual environment where the system will be
What is “digital gain scaling” and how is it operating, and may be desirable or even necessary
useful? for some systems.
The term “digital gain scaling” is used to describe The easiest way to implement a factory calibration
the way that the gain register in these converters is to write the system software so that it has two op-
can be manipulated to digitally scale a smaller in- erating modes: “calibration mode” and “user
put voltage over the entire output code range of the mode”. The normal operation mode when power-
ADC. Recall that the gain register can be varied ing on the system should be the user mode. In this
from 0 to 64 - 2-24, but should not exceed 40 (dec- mode, the system should perform all the functions
imal. Because the gain register can be manually relative to the end user. The calibration mode can
written and read, this function may be done within be entered with a hardware jumper setting, a soft-
the system software. In addition, the gain register ware switch, or any number of other options, but it
provides a very accurate means of changing the in- should not be a normal function for the user. In cal-
put span of the ADC without having to perform a ibration mode, the system can perform any neces-
new calibration. For example, the gain register can sary calibration and configuration tasks, and store
be read from the part, shifted left by 1 bit and writ- the results to some form of on-board, non-volatile
ten back into the part. This will have the effect of memory. An example of this is to use the on-chip
doubling the converter’s gain without introducing system calibration functions to perform offset and
any gain error, as changing the amplifier gain set- gain calibration, and then read the calibration re-
ting in the part would. Non-binary gain changes sults from the ADC and store them to EEPROM. In
can also be implemented using this type of gain user mode, the system would then read the registers
register manipulation. This allows for virtually any out of EEPROM and write the values into the
input voltage span between 5 mV and 2.5 V, using ADC’s registers on power-up to be used for normal
a combination of amplifier gain settings and gain operation.
register manipulation.
I need to be able to do a field calibration peri-
What are some different approaches to using odically on a weigh scale using calibration
calibration in my system? weights. Are the internal calibration registers
Calibration can be done at the manufacturing and useful for this type of calibration?
testing stage, or in the field. A calibration step done
The internal calibration registers can be very useful
at the manufacturing or testing stage is generally
in this type of calibration, though this may not be
referred to as a factory calibration, and is normally
obvious at first. The usual method of calibrating a
performed only once. A field calibration on the oth-
scale with calibration weights is to first zero-out the
er hand, may be done at any time when the system
scale with nothing on the platform, and then adjust
is in operation, either automatically or initiated by
the output of the scale to the correct reading once a
the user. Some systems may only use one type of
calibration weight has been placed on the platform.
calibration, where other systems may use a combi-
nation of both field and factory calibration. The ad- If the on-chip gain register is going to be used to ad-
vantage of a factory calibration is that it can usually just the scale’s output, the zero-point of the scale
should first be calibrated by setting the gain register

AN150REV2 9
 AN150

to 1.0 and performing a system offset calibration, vice every time. When the OGS bit in the Configu-
or adjusting the offset register until the scale reads ration Register is equal to ‘0’, the CS1-CS0 bits in
zero. Following this, the gain register can be adjust- the Setup are used to select the offset and gain reg-
ed to obtain the correct reading for the calibration isters that will be accessed.
weight. One way of doing this is to set the gain reg-
ister to a value that will give approximately the cor-
What is the difference between single and
rect reading from the scale, and perform a continuous conversion mode?
conversion (or multiple conversions) to get a dis- The most noticeable differences between these two
play output from the scale. The gain register can modes are the speed at which conversions can be
then be read from the part, and a value can be added performed, and whether the converter will begin a
or subtracted based on user input to adjust the gain new conversion when the current one is finished. In
register up or down. Once the gain has been adjust- continuous conversion mode, every conversion is
ed and written back into the ADC, another conver- output from the ADC, and the converter will con-
sion (or multiple conversions) can be performed to tinue to perform conversions until it is halted by the
get a new display output from the scale. This pro- system microcontroller. This includes any un-set-
cess can be repeated until the display output match- tled outputs from the sinc3 or sinc5 filter. Data is
es the desired value. In a more complex system, converted and output from the part at the output
this process may even be automated such that the word rate specified by the selected Setup. Continu-
user enters the magnitude of the calibration weight, ous conversion mode is most useful when perform-
and the system adjusts the gain register and takes ing conversions on a single channel for extended
readings until the value from the scale reads the periods of time. The very first output word of a con-
same as the desired calibration value. tinuous conversion cycle takes longer than subse-
quent conversions, due to some internal
How are the OG1-OG0 bits in the Channel synchronization of the converter.
Setup Registers used?
The single conversion mode is different in that the
The OG1-OG0 bits in the Channel Setup Registers digital filter processes the modulator bitstream un-
allow the system to select from any of the offset til it can compute a fully-settled result to output a
and gain registers available in the device when per- data word. A conversion in single conversion mode
forming conversions on a specific channel. Nor- therefore lasts longer than one performed in contin-
mally, the offset and gain registers associated with uous conversion mode. In addition, when a single
the currently selected physical channel (as speci- conversion is finished, the part will not perform an-
fied by CS1-CS0 in the Setup) are used when per- other conversion until a new conversion command
forming conversions. To tell the ADC that the is initiated. Single conversion mode is most useful
OG1-OG0 bits are to be used instead, a ‘1’ must be when repeatedly performing conversions on more
written to the Configuration Register’s OGS bit (bit than one channel of the part, or when using an ex-
20). Then, the offset and gain registers for the chan- ternal multiplexer.
nel specified by the OG1-OG0 bits will be used,
while the conversion is still performed on the chan- Note that the time to arrive at a fully-settled output
nel specified by CS1-CS0. This allows a system to from the part in continuous conversion mode is the
quickly access different gain and offset register set- same amount of time that a single conversion takes.
tings for conversions on the same physical channel,
without having to write those registers into the de-

10 AN150REV2
 AN150

Why is the “Common mode + signal on AIN+ fier cannot drive the voltage on the OUT+ or OUT-
or AIN-” specification different for the 1X pins below (VA- + 0.1 V) or above (VA+ - 0.1 V).
gain range? When either OUT+ or OUT- reaches or goes be-
yond these limits, the gain will become (2 × G)/(G
This difference is due to the fact that there are actu-
+ 1). To prevent this from happening, the front-end
ally two different amplifiers inside the converter. In
circuitry on the ADC should be designed to ensure
the 1X gain range, a rail-to-rail, unity-gain amplifi-
that both OUT+ and OUT- remain within these lim-
er is used. A rail-to-rail amplifier is necessary in the
its at all times.
1X gain range to permit the large input voltage
swings that are expected with this gain range. To How do I use the internal multiplexer in the
achieve the high level of performance typical of the part?
CS553x family in the 2X-64X gain ranges, a chop-
The different channels of the internal mux can be
per-stabilized, low-drift, multi-path amplifier is
selected using the Setups in the Channel Setup
used. The architecture of this amplifier does not
Registers. The most effective way of using the in-
permit rail-to-rail input capability. In the 2X-64X
ternal mux is to initiate two or more Setups with
gain ranges, input signals into the AIN+ and AIN-
different physical channel values, and then alter-
inputs must remain higher than (VA- + 0.7 V) and
nate between the Setups as needed while perform-
lower than (VA+ - 1.7 V) for accurate measure-
ing single conversions. Single conversion mode is
ments to occur.
recommended when using the internal mux if the
A further consideration is the output of the amplifi- user wants to switch between channels as quickly
er. Figure 1 shows a model of the PGIA. In addition as possible. No advantage is gained by using the
to the common mode requirements on the analog continuous conversion mode, since the settling
inputs, the user must ensure that the output of the time for this mode is the same as for the single con-
amplifier does not become saturated. Using the version mode, and it takes more software overhead
equations for VCM and VIN shown in Figure 1, the on the microcontroller’s part to start and stop the
voltages on the output of the amplifier (OUT+ and conversions. The single conversion mode will en-
OUT-) are equal to VCM ± (G × VIN)/2. The ampli- sure that each new conversion from the different
VA+ mux settings will produce a fully-settled result.
AIN+
OUT+ Continuous conversion mode can be useful, how-
VA- (G-1)xR
ever, if the user wants to convert a single channel
for long periods of time, and only periodically get
a sample from other channels. Data on a single
2xR channel can be collected much faster using this
mode.
VA+ (G-1)xR
How is the guard drive output pin used?
OUT-
AIN-
The A0 pin on the CS5531/32/33/34 has a dual
VA-
function as both a latch output and an output for the
(AIN+) + (AIN-) instrumentation amplifier’s common-mode volt-
V IN = (AIN+) - (AIN-) V CM =
2 age. The setting of the GB bit (bit 26) in the Con-
figuration Register controls which mode this pin is
Figure 1. Amplifier Model (2X-64X Gain) in. When the GB bit is ‘0’, the A0 pin functions as

AN150REV2 11
 AN150

an output latch pin. When the GB bit is set to ‘1’, part is in standby or sleep mode, the instrumenta-
the instrumentation amplifier’s common-mode tion amplifier is powered down.
voltage is output on the A0 pin. It is important to note that the guard drive output
The amplifier’s common-mode voltage is only out- typically can only source about 10-20 uA of drive
put on the A0 pin when the 2X-64X instrumenta- current. If the guard signal is used in an application
tion amplifier is on, and the device is in the normal which requires more drive current, an external
operating mode. On power-up, the instrumentation buffer should be used to provide the necessary cur-
amplifier is off by default. To engage the amplifier, rent. Also, the guard drive output should be protect-
a conversion or calibration must be started with the ed against high voltage or current spikes, if they are
part set up to use a gain from 2X to 64X. The am- likely to occur. Voltage or current spikes into the
plifier will remain on until a conversion or calibra- guard buffer can damage the ADC, and cause the
tion is performed in the 1X gain range. When the ADC to malfunction.

12 AN150REV2
• Notes •