International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882

43 EATHD-2015 Conference Proceeding, 14-15 March, 2015

DESIGN AND PERFORMANCE ANALYSIS OF AREA EFFICIENT

CMOS DECODER CIRCUIT
1
Vanshikha Singh, 2Rajesh Mehra
1
M.E.Scholar, 2Associate Professor
1,2
Departmant of Electronics & Communication Engineering
NITTTR, Chandigarh, UT, India

ABSTRACT CMOS stands for Complementary Metal Oxide Silicon

In recent years due to the magnificent development in technology is recognized as the leading VLSI systems
CMOS technology to reduce area and power of chip technology [2]. "CMOS" refers to both a particular style
designs take attention in research area. Decoder plays an of digital circuitry design and the family of processes
important role in the code conversion and encryption of used to implement that circuitry on integrated circuits
codes. It is having application in much area. A decoder (chips). CMOS circuits use a combination of p-type and
is used to change a code into a set of signals and n-type metal–oxide–semiconductor field-effect
translate the encoded data in its original form. In this transistors (MOSFETs) to implement logic gates and
paper Decoder has been designed and simulated using other digital circuits. For the most recent CMOS feature
different CMOS layouts. Design methodologies are used sizes, leakage power dissipation has become an
such as standard cell based design, semi custom design overriding concern for VLSI circuit design [3]. CMOS
and full custom design of the Decoder to reduce area, technology comprising the pull up and pull down
power and size of the circuit. The paper analyzes and network where pull up network consist PMOS and pull
optimizes area and power of the Decoder using 90 nm down network consist NMOS circuit. CMOS is used
technologies. The area gets reduced in full custom in microprocessors, microcontrollers, static RAM, and
design by 50.57% from standard layout and 42.68% other digital logic circuits.
from semi custom design. The complexity and area get Because of the combination of these thousands of
reduced in the full custom designed. CMOS transistors into a single plate to create a very
large integrated circuit. VLSI stands for "Very Large
Key Words: CMOS technology, Combinational circuits, Scale Integration" which includes packing more and
IC layout, Very large scale integration. more logic devices into smaller and smaller areas.
Digital VLSI circuits are predominantly CMOS based.
1. INTRODUCTION The huge chips that can be fabricated today are possible
only because of the extremely low power consumption
Electronic devices are extensively used in many different and smaller area of CMOS circuits [4].
fields and the size of these devices is gradually reduced.
This is due to the integrated circuit technology. 2. DECODER
An integrated circuit or monolithic integrated circuit is a
set of electronic circuits on one small plate called "chip" A decoder is a device which does the reverse operation
of semiconductor material, mostly silicon. Integrated of an encoder, decrypting the encoding so that the
circuits are used in virtually all electronic equipment original information can be fetched. It is a
today and have revolutionized the world of electronics. combinational circuit that converts binary information
In the growth of integrated circuit towards the large from n input lines to a maximum of 2n unique output
integration density with high operating frequency the lines. In digital electronics, a decoder can take the form
concern issues are power, delay and smaller silicon area of a multiple-input, multiple-output logic circuit that
with higher speed [1]. Computers, mobile phones, and converts encrypted inputs into decrypted outputs, where
other digital home appliances are now inextricable parts the input and output codes are different. Enable inputs
of the structure of modern societies, made possible by must be on for the decoder to function, otherwise its
the low cost of integrated circuits. ICs have two main outputs assume a single "null" output code word. Logic
advantages over discrete circuits which is cost and design is guided by the requirements imposed on the
performance. There is the technology which is used to implementation, such as performance and power [5].
construct integrated circuit which is CMOS technology. Decoding is necessary in applications such as data
multiplexing, 7 segment display and memory address

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
44 EATHD-2015 Conference Proceeding, 14-15 March, 2015

decoding. Decoder circuit would be an AND Fig.2 shows the circuit diagram of the decoder. In this
gate because the output of an AND gate is "High" (1) diagram we realized the decoder expression using NOT
only when all its inputs are "High." Such output is called gate and AND gate. The output is in term of the
as "active High output". If instead of AND gate, the combination of the inputs. We have two inputs A and B
NAND gate is connected the output will be "Low" (0) and the outputs are D0, D1, D2, and D3. The Expression
only when all its inputs are "High". Such output is called for the outputs is given as under:
as "active low output". A slightly more complex decoder
would be the n-to-2n type binary decoders. These types D0 = A’B’ (1)
of decoders are combinational circuits that convert D1 = A’B (2)
binary information from 'n' coded inputs to a maximum D2 = AB’ (3)
of 2n unique outputs. We can have 2-to-4 decoder, 3-to-8 D3 = AB (4)
decoder or 4-to-16 decoder.
Table.1 Truth Table of 2 bit Decoder

INPUT OU.TPUT

A B D0 D1 D2
D3

0 0 1 0 0
0
0 1 0
0 1 0
Fig. 1 Block Diagram of 2 bit Decoder
1 0 0 0 1
Fig. 1 Shows the Block diagram of 2 bit Decoder. In this 0
diagram we have two inputs and four outputs. The
output is decided according to the priority of inputs. The 1 1 0 0 0
output which is the combination of low logic of inputs is 1
set as lowest priority output and the output which is the
combination of high logic of inputs is set as highest Table.1 Shows the Truth table of Decoder. In this table,
priority output. Decoder plays important role in the according to the inputs the output is shown. The output
communication system [10]. D0 is high when both the input is low. The outputs D1
and D2 are high when one of the inputs is low. The
output D3 is high when both the input is high.

3. SIMULATION AND RESULTS

Design processes are aided by simple concepts such as

stick and symbolic diagrams but the key element is the
design rules. Design rules are used to produce the
workable mask layouts from which the various layers in
silicon will be formed or patterned [6]. Complementary
metal–oxide–semiconductor (CMOS) technology is
being used in various digital and analog logic circuits
such as image sensors (CMOS sensor), data converter
circuits and decoding circuits [7]. The Schematic
Diagram of 2:4 Decoders is given in Fig. 3. This
Fig. 2 Circuit Diagram of 2 bit Decoder diagram constructed by using two inverters and four
AND gate. The input is in the form of switch and the

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
45 EATHD-2015 Conference Proceeding, 14-15 March, 2015

corresponding output is shown by glowing of LED

connected at the outputs.

Fig. 5 Standard layout of 2 bit Decoder

Fig. 5 shows auto generated Standard layout of 2 bit

Decoder. In this layout we have pull up and pull down
Fig. 3 Schematic Diagram of 2 bit Decoder network having CMOS technology. This Standard layout
is very complex and consumes more area. Fig. 6 shows
the corresponding simulated result of Standard Layout.

Fig. 4 Simulation Result of Schematic of 2 bit Decoder

Fig. 6 Simulation Result of Standard Layout
Fig. 4 shows the simulated result of the Schematic
diagram of the 2 bit decoder. In Fig. we have two inputs Fig. 7 shows semi custom layout of 2 bit Decoder. In
and four outputs. The inputs are in the form of two this layout we take PMOS and NMOS which already
clocks and the output is varying according to the input exists in library of the software. By using these PMOS
clocks. and NMOS circuit we design the logic gates by self. In
decoder two inverter and four and gate are needed. So
we design AND gate with the help of self design NAND
gate and inverter. The inverters are constructed in form
of pull up and pull down network using PMOS and
NMOS. This semi custom design is less complex using
less area and power. Fig. 8 shows the corresponding
simulated waveform of Semi custom Layout.

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
46 EATHD-2015 Conference Proceeding, 14-15 March, 2015

Fig. 9 shows full custom layout of 2 bit Decoder. In this

layout we make PMOS and NMOS by itself using the
diffusion element, metal, polysilicon, and well existing
in the library. By using these PMOS and NMOS circuit
we design the logic gates by self. In decoder two inverter
and four and gate are needed. So we design AND gate
with the help of self design NAND gate and inverter.
The inverters are constructed in form of pull up and pull
down network using PMOS and NMOS. This design is
less complex and using less area in the layout but delay
is more [8]. Fig.10 shows the corresponding simulated
waveform of full custom Layout.

Fig. 7 Semi custom layout of 2 bit Decoder

Fig. 10 Simulation waveform of full custom layout

4. COMPARITIVE ANALYSIS
Fig. 8 Simulation waveform of Semi custom layout
In this paper the decoder is designed by the three
different layout using CMOS technology. The three
decoder layouts are the standard cell based design
layout, semi custom based design layout and full custom
based design layout.
The main parameters of consideration for analysis are
area, complexity and power of the 2 bit Decoder design
in this paper. Table 2 show the area and power
consumption of 2 bit design using CMOS technology.
Fig. 11 and Fig. 12 show the comparative analysis of
power and area of different layout respectively.

Fig. 9 Full custom layout of 2 bit Decoder

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
47 EATHD-2015 Conference Proceeding, 14-15 March, 2015

5. CONCLUSION
Table 2 Area and Power consideration
Today’s integrated circuits have a growing need for
speed, area, and power. Despite many advantages,
DECODER TECHNOLO AREA POWE CMOS suffers from increased area, more power
LAYOUTS GY USED R dissipation and correspondingly increased capacitance
and delay, as the logic gates become more complex
[9].So we have to develop and simulate the those layouts
Standard 90 nm 700.4 99.19 which consume less area and power. It has been
cell based um2 μW demonstrated from the simulated results of different
design layout that the area is reduced in the full custom design
of the decoder circuit from standard cell layout and the
semi custom based layout of the decoder. The power is
Semi 90 nm 604.2 81.57
reduced in the semi custom design from standard cell
custom um2 μW
layout but increased in the full custom design. So
based
reduction of power in the full custom design is the future
design
aspect.
Full 90 nm 346.3 99.87
ACKNOWLEDGEMENT
Custom um2 μW
Design
The authors would also like to thank Director, National
Institute of Technical Teachers’ Training & Research,
Chandigarh, India and H.R. Institute of Technology,
Ghaziabad for their constant inspirations and support
throughout this research work.

REFERENCES

[1] Swati Sharma, Rajesh Mehra, “Area And Power

Efficient Design Of XNOR-XOR Logic Using 65 nm
Technology”, International Journal Of Engineering And
Technical Research ISSN: 2321-0869, pp. 57-60, STET-
2014.
[2] “Neil H.E. Weste, Kamran Eshraghian”, “Principles
of CMOS VLSI Design, A System Perspective”, Second
Fig.11 Power of different layout 2 bit Decoder Edition, pp. 117-118.
[3] Pushpa Saini, Rajesh Mehra,“Leakage Power
Reduction in CMOS VLSI Circuits”, International
Journal of Computer Application, Volume 55-no.8, pp.
42-48, October 2012.
[4] “Wayne Wolf”, “Modern VLSI Design, System-on-
Chip Design”, Third Edition, pp. 36-37, 2000.
[5] “Wayne Wolf”, “FPGA-Based System Design”, pp.
181-182.
[6] Douglas A. Pucknell, Kamran Eshraghian, “Basic
VLSI Design”, Third Edition, pp. 56-57, 2009.
[7] Pooja Singh, Rajesh Mehra, “Design Analysis of
XOR Gates Using CMOS & Pass Transistor”
International Journal of Engineering Science Invention
Research & Development, Vol. 1 Issue 1, pp.21-25, July
2014.
Fig.12 Area of different layout 2 bit Decoder

Shanti Institute of Technology, Meerut (U.P.) - 250501, India

 International Journal of Scientific Research Engineering & Technology (IJSRET) ISSN: 2278–0882
48 EATHD-2015 Conference Proceeding, 14-15 March, 2015

[8] K R Viveka and Bharadwaj Amrutur, “Energy

Efficient Memory Decoder Design For Ultra Low
Voltage Systems”, 27th international conference on VLSI
Design and 13th international conference on embedded
systems, pp. 145-149, 2014.
[9] Akhilesh Verma, Rajesh Mehra,“Design and
Analysis of Conventional and Ratioed Cmos Logic
Circuit” IOSR Journal of VLSI and Signal Processing
Vol.2, pp. 25-29, April 2013.
[10] W. Li and Z. C. Zhu, “Encoder And Decoder
Design For Fault Detection Over Networks” IEEE,
International Conference On Control Applications, pp.
1785-1789, September, 2010.

AUTHORS
Vanshikha Singh received the
Bachelors of Technology degree in
Electronics and Communication
Engineering from Chandra Shekhar
Azad University, Kanpur, India in
2010.She is pursuing Master of
Engineering degree in Electronics and
Communication Engineering from
National Institute of Technical Teachers’ Training &
Research, Punjab University, Chandigarh, India.

Rajesh Mehra received the Bachelors

of Technology degree in Electronics
and Communication Engineering from
National Institute of Technology,
Jalandhar, India in 1994, and the
Masters of Engineering degree in
Electronics and Communication
Engineering from National Institute of Technical
Teachers’ Training & Research, Punjab University,
Chandigarh, India in 2008. He is pursuing Doctor of
Philosophy degree in Electronics and Communication
Engineering from National Institute of Technical
Teachers’ Training & Research, Punjab University,
Chandigarh, India.
He is an Associate Professor with the Department of
Electronics & Communication Engineering,, National
Institute of Technical Teachers’ Training & Research,
Ministry of Human Resource Development, Chandigarh,
India. His current research and teaching interests are in
Signal, and Communications Processing, Very Large
Scale Integration Design. He has authored more than
175 research publications including more than 100 in
Journals. Mr. Mehra is member of IEEE and ISTE.

Shanti Institute of Technology, Meerut (U.P.) - 250501, India