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EM MICROELECTRONIC-MARIN SA
V3021
Ultra Low Power 1-Bit 32 kHz RTC

Features Typical Operating Configuration

n Supply current typically 800 nA at 3 V
n 50 ns access time with 50 pF load capacitance

WR or R/W
n Fully operational from 2.0 V to 5.5 V

RD or DS
n No busy states or danger of a clock update while
accessing CPU
n Serial communication on one line of a standard parallel
data bus or over a conventional 3 wire serial interface
n Interface compatible with both Intel and Motorola
n Seconds, minutes, hours, day of month, month, year, week Address
day and week number in BCD format Decoder
n Leap year and week number correction
n Time set lock mode to prevent unauthorized setting of the

ADDRESS BUS
current time or date XI
CS
n Oscillator stability 0.3 ppm / volt DATA BUS
n No external capacitor needed RD XO
WR
n Frequency measurement and test modes
V3021
n Temperature range - 40 to +85 oC
I/O
n Packages DIP8 and SO8

Description
RAM
The V3021 is a low power CMOS real time clock. Data is CS
RD
transmitted serially as 4 address bits and 8 data bits, over one WR
line of a standard parallel data bus. The device is accessed by
chip select (CS) with read and write control timing provided by
either RD and WR pulse (Intel CPU) or DS with advanced R/W
Fig. 1
(Motorola CPU). Data can also be transmitted over a
conventional 3 wire serial interface having CLK, data I/O and
strobe. The V3021 has no busy states and there is no danger of Pin Assignment
a clock update while accessing. Supply current is typically 800
nA at VDD = 3.0 V. Battery operation is supported by complete DIP8 / SO8
functionality down to 2.0 V. The oscillator stability is typically 0.3
ppm/V.

XI VDD
Applications
XO WR
n Utility meters V3021
n Battery operated and portable equipment CS RD
n Consumer electronics VSS I/O
n White/brown goods
n Pay phones
n Cash registers
n Personal computers
n Programmable controller systems
n Data loggers
Fig. 2
n Automotive electronics

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V3021
Absolute Maximum Ratings be taken as for any other CMOS component. Unless otherwise
specified, proper operation can only occur when all terminal
Parameter Symbol Conditions voltages are kept within the supply voltage range. Unused
Maximum voltage at VDD VDDmax VSS + 7.0 V inputs must always be tied to a defined logic voltage level.
Minimum voltage at VDD VDDmin VSS - 0.3 V
Maximum voltage at any signal pin Vmax VDD + 0.3 V
Minimum voltage at any signal pin Vmin VSS - 0.3 V Operating Conditions
Maximum storage temperature TSTOmax +150 OC
Minimum storage temperature TSTOmin -65 OC Parameter Symbol Min. Typ . Max. Units
O
Electrostatic discharge maximum Operating temperature TA -40 +85 C
to MIL-STD-883C method 3015 VSmax 1000 V Logic supply voltage VDD 2.0 5.0 5.5 V
Maximum soldering conditions TSmax 250 OC x 10 s Supply voltage dv/dt
(power-up & power-down) 6 V/ms
Table 1
Stresses above these listed maximum ratings may Decoupling capacitor 100 nF
cause permanent damage to the device. Exposure Crystal Characteristics
1)
beyond specified operating conditions may affect Frequency f 32.768 kHz
device reliability or cause malfunction. Load capacitance CL 7 8.2 30 pF
Series resistance RS 35 50 kW
Handling Procedures 1)
See Fig. 3 Table 2
This device has built-in protection against high static voltages
or electric fields; however, it is advised that normal precautions

Electrical Characteristics
VDD = 5.0V ± 10%, VSS = 0 V and TA = - 40 to 85 OC, unless otherwise specified

Parameter Symbol Test Conditions Min. Typ. Max. Units

Total static supply ISS all outputs open, all inputs at VDD 0.8 1.8 mA
VDD = 3.0 V, address 0 = 0
Total static supply ISS all outputs open, all inputs at VDD, 1.3 10 mA
VDD = 5 V, address 0 = 0
TA = +25OC 3 mA
Dynamic current ISS I/O to VSS through 1 MW 300 mA
RD = VSS, WR = VDD,
CS = 4 MHz
address 0 = 0, read all 0
Input / Output
Input logic low VIL 1.0 V
Input logic high VIH 3.5 V
Output logic low VOL IOL = 4 mA 0.4 V
Output logic high VOH IOH = 4 mA 2.4 V
Input leakage IIN 0.0 < VIN < 5.0 V 0.1 1 mA
Output tri-state leakage ITS CS high, and address 0, 0.1 1 mA
on I/O pin bit 0, low

Oscillator
Starting voltage VSTA 1.8 V
Input capacitance on XI CIN TA = +25 OC 13 pF
Output capacitance on XO COUT TA = +25 OC 9 pF
Start-up time TSTA 1 s
Frequency stability Df/f 2.0 £ VDD £ 5.5V , TA = +25 OC 0.3 0.5 ppm/V
Frequency Measurement Mode
Current source on I/O pin IONF CS high, addr.0, bit 0, high 10 25 60 mA
pulsed on/off @ 256 Hz VI/O = 1 V
Table 3

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V3021
The V3021 will run slightly too fast, in order to allow the user to between XO and VSS. The printed circuit capacitance has also to
adjust the frequency, depending on the mean operating be taken in consideration. The V3021 in DIL8 package, running
temperature. This is made since the crystal adjustment can only with an 8.2 pF crystal at room temperature, will be adjusted to
work by lowering the frequency with an added capacitor better than ± 1 s/day with a 6.8 pF capacitor.

Typical Frequency on I/O Pin

DF
[ppm] Address 10 hex = 00 hex Quartz with 8.2 pF load capacitance
Fo s/day
80 3

30 2

-20 1

-70 0

-120 -1

-170 -2
-50 -30 -10 10 30 50 70 90 0 3 6 9 12 15
TA [O C] External trimming capacitor between XO and VSS [pF]
Typical drift for ideal 32'768 Hz quartz
Note : The trimming capacitor value must not exceed 15 pF.
Greater values may disturb the oscillator function.

Fig. 3

Quartz Characteristics

DF
F0 DF ppm 2
Fo = - 0.038 OC2 (T - TO) ±10%
[ppm]
-100
DF/Fo = the ratio of the change in frequency to the nominal value
Frequency ratio [ppm]

expressed in ppm (It can be thought of as the frequency

deviation at any temperature.)
-200
T = the temperature of interest in OC
x.
ma

TO = the turnover temperature (25 ± 5 OC)

.
min

-300
To determine the clock error (accuracy) at a given temperature, add
the frequency tolerance at 25OC to the value obtained from the
-400 formula above.
TO-100 TO-50 TO TO+50 TO+100
O
Temperature [ C] T [OC]

Fig. 4

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V3021
Timing Characteristics
VSS = 0 V, and TA = - 40 to +85 OC, unless otherwise specified

Parameter Symbol Test Conditions Min. Max. Min. Typ. Max. Units
VDD ³ 2 V VDD = 5.0V ± 10%
Chip select duration tCS Write cycle 200 50 ns
1)
RAM access time tACC CLOAD = 50 pF 180 50 60 ns
Time between two transfers tW 500 100 ns
2)
Rise time tR 10 200 10 200 ns
2)
Fall time tF 10 200 10 200 ns
Data valid to Hi-impedance
3)
tDF 10 100 15 30 40 ns
4)
Write data settle time tDW 60 50 ns
5)
Data hold time tDH 80 25 ns
Advance write time tADW 25 10 ns
6)
Write pulse time tWC 200 50 ns
1) Table 4
tACC starts from RD or CS, whichever activates last
Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF
2)
CS, RD, DS, WR and R/W rise and fall times are specified by tR and tF
3)
tDF starts from RD or CS, whichever deactivates first
4)
tDW ends at WR or CS, whichever deactivates first
5)
tDH starts from WR or CS, whichever deactivates first
6)
tWC starts from WR or CS, whichever activates last and ends at WR or CS, whichever deactivates first

Timing Waveforms
Read Timing for Intel (RD and WR Pulse) and Motorola (DS (or RD pin tied to CS) and R/W)

tCS tW
tR tF
CS
tACC
RD / DS

WR / R/W
tDF
I/O data valid
Fig. 5a

Write Timing for Intel (RD and WR Pulse)

tCS tW

CS

RD
tWC
WR
tDW tDH
I/O
data valid
Fig. 5b

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V3021
Write Timing for Motorola (DS (or RD pin tied to CS) and R/W)
tCS tW

CS

DS
tADW
R/W
tDW tDH

I/O data valid Fig. 5c

Communication Cycles
Read Data Cycle for Intel (RD and WR Pulse)

CS
DS

WR

I/O A0 A1 A2 A3 D0 D1 D7

mP writes 4 address bits mP reads 8 data bits

Fig. 6a

Read Data Cycle for Motorola (DS (or RD Pin Tied to CS) and R/W)

CS
DS

R/W

I/O A0 A1 A2 A3 D0 D1 D7

mP writes 4 address bits mP reads 8 data bits

Fig. 6b

Write Data Cycle for Intel (RD and WR Pulse)

CS

RD “ 1”
“ 0”
WR

I/O A0 A1 A2 A3 D0 D1 D7

mP writes 4 address bits mP reads 8 data bits

Fig. 6c

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V3021
Write Data Cycle for Motorola (DS (or RD Pin Tied to CS) and R/W)

CS
DS

R/W

I/O A0 A1 A2 A3 D0 D1 D7

mP writes 4 address bits mP reads 8 data bits

Fig. 6d

Address Command Cycle for Intel Address Command Cycle for Motorola
(RD and WR Pulse) (DS (or RD Pin Tied to CS) and R/W)

CS CS
“1” DS
RD
“0”
WR R/W

A0 A1 A2 A3 I/O A0 A1 A2 A3
I/O
mP writes 4 address bits mP writes 4 address bits
Fig. 6e Fig. 6f

Block Diagram

XI
Oscillator and
XO Divider Chain
1Hz

Clock
(reserved Tue 2
area) mEM

0 Status 0
1 Status 1
2
-
-
RAM - Mon 1
(user RAM
- mEM
area) -
9
E Copy_RAM_to_clock
F Copy_clock_to_RAM
Read
Write
addr
data

I/O Serial Buffer RD

CS & Decoder WR

Fig. 7

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V3021
Pin Description Address Command Cycle
An address command cycle consists of just 4 address bits. The
Pin Name Function
LSB, A0, is transmitted first (see Fig. 6e and 6f). On writing the
fourth address bit, A3, the address will be decoded. If the
1 XI 32 kHz crystal input address bits are recognized as one of the command codes
2 XO 32 kHz crystal output
E hex or F hex (see Table 6), then the communication cycle is
3 CS Chip select input
terminated and the corresponding command is executed.
4 VSS Ground supply
Subsequent microprocessor writes to the V3021 begin another
5 I/O Data input and output
communication cycle with the first bit being interpreted as the
6 RD Intel RD, Motorola DS (or tie to CS)
address LSB, A0.
7 WR Intel WR, Motorola R/W
8 VDD Positive supply Clock Configuration
The V3021 has a reserved clock area and a user RAM area (see
Table 5
Fig. 7). The clock is not directly accessible, it is used for internal
Functional Description time keeping and contains the current time and date. The
Serial Communication contents of the RAM is shown in Table 6, it contains a data space
The V3021 resides on the parallel data and address buses as a and an address command space. The data space is directly
standard peripheral (see Fig. 13 and 14). Address decoding accessible. Addresses 0 and 1 contain status information ( see
provides an active low chip select (CS) to the device. For Intel Tables 7a and 7b), addresses 2 to 5, time data, and addresses 6
compatible bus timing the control signals RD and WR pulse and and 9, date data. The address command space is used to issue
CS are used for a single bit read or write (see Fig. 5a and 5b). commands to the V3021.
Two options exist for Motorola compatible bus timing. The first RAM Map
is to use the control signals DS with R/W and CS, the second is
to tie the RD input to CS and use the control signals R/W and CS Address Parameter BCD
(see Fig. 5a and 5c). Data transfer is accomplished through a Dec Hex range
single input / output line (I/O). Any data bus line can be chosen. Data Space
A conventional 3 wire serial interface can also be used to 0 0 Status 0
communicate with the V3021 (see Fig. 15). 1 1 Status 1
Communication Cycles 2 2 Seconds 00-59
The V3021 has 3 serial communication cycles. These are : 3 3 Minutes 00-59
1) Read data cycle 4 4 Hours 00-23
2) Write data cycle 5 5 Day of month 01-31
3) Address command cycle 6 6 Month 01-12
A communication cycle always begins by writing the 4 address 7 7 Year 00-99
bits, A0 to A3. A microprocessor read from the V3021 cannot 8 8 Week day 01-07
begin a communication cycle. Read and write data cycles are 9 9 Week number 00-52
similar and consist of 4 address bits and 8 data bits. The 4 Address Command Space
address bits, A0 to A3, define the RAM location and the 8 data 14 E Copy_RAM_to_clock
bits, D0 and D7, provide the relevant information. An address 15 F Copy_clock_to_RAM
command cycle consists of only 4 address bits.
Table 6
Read Data Cycle
A read data cycle commences by writing the 4 RAM address Commands
bits (A3, A2, A1 and A0) to the V3021. The LSB, A0, is Two commands are available (see Table 6). The
transmitted first (see Fig. 6a and 6b). Eight microprocessor Copy_RAM_to_clock command is used to set the current time
reads from the V3021 will read the RAM data at this address, and date in the clock and the Copy_clock_to_RAM command to
beginning with the LSB, D0. The read data cycle finishes on copy the current time and date from the clock to the RAM. The
reading the 8th data bit, D7. Copy_RAM_to_clock command, address data E hex, causes
Write Data Cycle the clock time and date to be overwritten by the time and date
stored in the RAM at addresses 2 to 9. Address 1 is also cleared
A write data cycle commences by writing the 4 RAM address
(see section “Time and Date Status Bits”). Prior to using this
bits (A3, A2, A1 and A0) to the V3021. The LSB, A0, is
command, the desired time and date must be loaded into the
transmitted first (see Fig. 6c and 6d). Eight microprocessor
RAM using write data cycles and the time set lock bit, address 0,
writes to the V3021 will write the new RAM data. The LSB, D0, is
bit 7, must be clear (see section “ Time Set Lock”).
loaded first. The write data cycle finishes on writing the 8th data
bit, D7.

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V3021
Status Information On first startup or whenever power has failed (VDD < 2.0 V) the
The RAM addresses 0 and 1 contain status and control data for status register 0 and the clock must be initialized by software.
the V3021. The function of each bit (0 and 7) within address Having initialized the interface to expect the address bit A0,
locations 0 and 1 is shown in Tables 7a and 7b respectively. write 0 to status register 0, then set the clock (see section “Clock
and Calendar”).
Status Word
Time and Date Status Bits
Status 0 - address 0 There are time and date status bits at address 1 in the RAM.
Upon executing a Copy_clock_to_RAM command, the time and
0 - inactive
7 6 5 4 3 2 1 0 date status bits in the RAM show which time and date
1 - active
Read / Write bits parameters changed since the last time this command was
Frequency Measurement Mode used. A logic 1 in the seconds status bit (address 1, bit 0) in the
Reserved RAM indicates that the seconds location in the RAM (address 2)
Test Mode 0 changed since the last Copy_clock_to_RAM command and
Test Mode 1 thus needs to be read. The seconds location must change
Time Set Lock before any other time or date location can change. If the
Reserved seconds status bit is clear, then no time or date location
Reserved
changed since the last Copy_clock_to_RAM command and so
Reserved
the RAM need not to be read by software.
Table 7b shows the seconds, minutes, hours, day of the month,
Table 7a
month, year, week day, and week number status bit locations.
0 - No change from last They are set or cleared similar to the seconds location. It should
Status 1 - address 1
Copy_clock_to_RAM be noted that if the minutes status bit is clear, then the seconds
7 6 5 4 3 2 1 0 1 - Change from last bit may be set, but all other status bits are clear. Similarly with
Read ONLY bits Copy_clock_to_RAM hours, the bits representing the units less than hours may have
been set, but the bits for the higher units will be clear. This rule
Seconds
Minutes holds true for the week day or day of month locations also.
Hours The time and date status bits can be used to drive software
Day of month routines which need to be executed every
Month - second,
Year - minute,
Week day - hour,
Week number - day of month / week day,
- month,
Table 7b - year,
or - week.
Reset and Initialization In this application it is necessary to poll the V3021 at least once
Upon microprocessor recovery from a system reset, the V3021 every time interval used as it does not generate an interrupt.
must be initialized by software in order to guarantee that it is Upon executing a Copy_RAM_to_clock command, the time and
expecting a communication cycle (i.e the internal serial buffer is date status bits in the RAM are cleared.
waiting for the address bit A0). Software can initialize the V3021
to expect a communication cycle by executing 8
microprocessor reads (see Fig. 8).
Time Set Lock
The time set lock control bit is located at address 0, bit 4 (see
Initializing Access to the V3021 Table 7a). When set by software, the bit disables the
Copy_RAM_to_clock command (see section “Commands”.) A
set bit prevents unauthorized overwriting of the current time and
CS date in the clock. Clearing the time set lock bit by software will
RD re-enable the Copy_RAM_to_clock command. On first startup
or whenever power has failed (VDD < 2.0 V), the time set lock bit
WR must be setup by software.
I/O D0 D1 D7
mP reads 8 times
Fig. 8

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V3021
Reading the Current Time and Date will indicate which time and date addresses changed since the
last time the command was used (see Fig. 9). The time and date
from the last Copy_clock_to_RAM command is held
unchanged in the RAM, except when power (VDD) has failed

Send copy_clock_to_RAM addr. F hex totally. To change the current time and date in the clock, the
desired time and date must first be written to the RAM, the time
set lock bit cleared, and then a Copy_RAM_to_clock command
sent (see Fig. 10). The time set lock bit can be used to prevent
Read time and data status bits, addr. 1
unauthorized setting of the clock.

Setting the Current Time and Date

Is the seconds No
status bit set, Write seconds, minutes, hours, day
addr. 1, bit 0
of month, week day, month, year
and week number to the RAM
Yes
Clear the time set lock bit, addr. 0, bit 4
Read seconds, addr. 2

Send a copy_RAM_to_clock command,

addr. E hex

Is the minutes No
status bit set, Set the time set lock bit, addr. 0, bit 4
addr. 1,
bit 1
Fig. 10
Yes

Read minutes addr. 3 Frequency Measurement

Setting bit 0 at address 0 will put a pulsed current source (25 mA)
onto the I/O pin, when the device is not chip selected (i.e. CS
Similar for hours, day of month, input high). The current source will be pulsed on/off at 256 Hz.
week day, month, year and The period for ± 0 ppm time keeping is 3.90625 ms. To measure
week number the frequency signal on pin I/O, the data bus must be high
impedance. The best way to ensure this is to hold the
microprocessor and peripherals in reset mode while measuring
Current time and date the frequency. The clarity of the signal measured at pin I/O will
Fig. 9 depend on both the probe input impedance (typically 1 MW)
and the magnitude of the leakage current from other devices
Clock and Calendar driving the line connected to pin I/O. If the signal measured is
The time and date addresses in the RAM (see Table 6) provide unclear, put a 200 kW resistor from pin I/O to VSS. It should be
access to the seconds, minutes, hours, day of month, month,
noted that the magnitude of the current source (25 mA) is not
year, week day, and week number. These parameters have the
sufficient to drive the data bus line in case of any other device
ranges indicated on Table 6 and are in BCD format. If a
driving the line, but it is sufficient to take the line to a high logic
parameter is found to be out of range, it will be cleared on its
level when the data bus is in high impedance.
being next incremented. The V3021 incorporates leap year Use a crystal of nominal CL = 8.2 pF as specified in the section
correction and week number calculation. The week number
“Operating Conditions”. The MX series from Microcrystal is
changes only at the incrementation of the day number from 7 to
recommended. The accuracy of the time keeping is dependent
1. If week 52 day 7 falls on the 25th, 26th or 27th of December,
upon the frequency tolerance and the load capacitance of the
then the week number will change to 0 otherwise it will be week
crystal. 11.57 ppm correspond to one second a day.
1. Week days are numbered from 1 to 7 with Monday as 1.
Reading of the current time and date must be preceded by a
Copy_clock_to_RAM command. The time and date status bits

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V3021
Test
From the various test features added to the V3021 some may be
activated by the user. Table 7a shows the test mode bits. Table 8 XI
shows the 3 available test modes and how they can be 0 - 5.5 V 1)
activated. Test mode 0 is activated by setting bit 2, address 0, 100 kW V3021
and causes all time keeping to be accelerated by 32. Test mode XO
1 is activated by setting bit 3, address 0, and causes all the time 1)
56 kW
and date locations, address 2 to address 9, to be incremented
in parallel at 1 Hz with no carry over (independent of each
other). The third test mode combines the previous two resulting VSS 1)
indicative values
in parallel incrementing at 32 Hz. Fig. 11b

Test Modes Note : The peak value of the signal provided by the signal
generator should not exceed 2 V on XO.
Addr. 0 Addr. 0
Function
bit 3 bit 2 Crystal Layout
0 0 Normal operation In order to ensure proper oscillator operation we recommend
0 1 All time keeping accelerated by 32 the following standard practices:
1 0 Parallel increment of all time - Keep traces as short as possible.
data at 1 Hz with no carry over - Use a guard ring around the crystal.
1 1 Parallel increment of all time data Fig. 12 shows the recommended layout.
at 32 Hz with no carry over
Oscillator Layout
Table 8

An external signal generator can be used to drive the divider

chain of the V3021. Fig. 11a and 11b show how to connect the
signal generator. The speed can be increased by increasing the XI
signal generator frequency to a maximum of 128 kHz. An
external signal generator and test modes can be combined.
XO V3021
To leave test both test bits (address 0, bits 2 and 3) must be
cleared by software. Test corrupts the current time and date and CS
so the time and date should be reloaded after a test session. Vss
Fig. 12

Signal Generator Connection Access Considerations

The section “Communication Cycles” describes the serial data
sequences necessary to complete a communication cycle. In
XI common with all serial peripherals, the serial data sequences
1-2 V peak to peak are not re-entrant, thus a high priority interrupt, or another
V3021
software task, should not attempt to access the V3021 if it is
XO
already in the middle of a cycle. A semaphore (software flag) on
access would allow the V3021 to be shared with other software
tasks or interrupt routines. There is no time limit on the duration
VSS of a communication cycle and thus interrupt routines (which do
not use the V3021) can be fully executed in mid cycle without
Fig. 11a any consequences for the V3021.
Note : The peak value of the signal provided by the signal
generator should not exceed 2 V on XO.

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V3021
Typical Applications
V3021 Interfaced with Intel CPU (RD/WR Pulse)

BUS A/D 0-7

D0
BUS ADDRESS A8-A15
8088 to other peripherals
Decoder and memory
WR
RD

CS RD WR I/O

V3021

Fig. 13

V3021 Interfaced with Motorola CPU (Advanced R/W)

BUS A/D 0-7

D0
BUS ADDRESS A8-A15
68000
to other peripherals
Decoder and memory
R/W
LDS

CS RD WR I/O

V3021

Fig. 14

3 Wire Serial Interface

1) With strobe low bits are written to the V3021, and

µP CS µP CS with strobe high bits are read from the V3021
VSS 2) For serial ports with byte transfer only, an address
V3021 V3021 command cycle should be combined with every
CLK data cycle to give 8 address bits and 8 data bits. For
RD Port A.0 WR
DATA example to read the current minutes, write address
I/O Port A.1 RD
Strobe data F + 3 (1111 + 0011) and then read 8 data bits.
WR Port A.2
1) & 2) I/O
Fig. 15

Battery Switch Over Circuit

+5V
BAT85*
VDD +5V * Use Schottky barrier diodes. The
BAT85 has a typical VF of 250 mV at an
iF of 1 mA.
1MW BAT85* The reverse current is typically 200 nA
at a VR of 5 V. The reverse recovery time
V3021
is 5 ns. For surface mount applications
+3 V
use the Philips BAT17 in SOT-23 or
other.
VSS
CS I/O D0 of data bus
Motorola BS107A or 3N171
Fig. 16

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V3021
Ordering Information
The V 3021 is available in the following package :
DIP8 plastic package V3021 8P
SO8 plastic package V3021 8S

When ordering, please specify the complete part number.

EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in
an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications
without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date
Ó 2000 EM Microelectronic-Marin SA, 10/00, Rev. K/331

EM MICROELECTRONIC-MARIN SA, CH-2074 Marin, Switzerland, Tel. +41 32 - 755 51 11, Fax +41 32 - 755 54 03
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