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(ECE) /HD Examination: Se:Vleste

1) Differentiates between mental delay and transport delay with an example, describing a 4-bit full adder using generate statements in structural modeling, and declaring an integer data type to create a 512-byte memory with 8 address lines. 2) Describes the values of statements with given inputs and writes a VHDL process equivalent to a concurrent statement. 3) Writes a VHDL description of a DD flip-flop with direct set and reset inputs that can change state on both rising and falling clock edges, and makes a timing table showing the values of signals in two given VHDL processes over time.

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79 views1 page

(ECE) /HD Examination: Se:Vleste

1) Differentiates between mental delay and transport delay with an example, describing a 4-bit full adder using generate statements in structural modeling, and declaring an integer data type to create a 512-byte memory with 8 address lines. 2) Describes the values of statements with given inputs and writes a VHDL process equivalent to a concurrent statement. 3) Writes a VHDL description of a DD flip-flop with direct set and reset inputs that can change state on both rising and falling clock edges, and makes a timing table showing the values of signals in two given VHDL processes over time.

Uploaded by

Ranveer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll No .

BE (ECE)
\HD SE:VlESTER EXAMINATION (September-2018)
F:CD-14 : Digital System Design Using VHDL/V \!rilog

fimt ·· 1· 3P, Hour.')


Max. M~rks: 15
'rHe: AH . .
questions car~, equal marks. Assume suitable missing data, if any .
I,
(1+3+l=5 )
~ Dihprenuat b · ·
- e e1ween menial delay and transport delay with the help of sunabk
example
\,, me 3 'H DL coae tor b4-bit I-ull Adder using Generate Statement in Structural
modelling
Declare ar. integer data type to create a memory of 512 bytes with 8 address lines.

ff I
(1 +1+2+ J=5)
. ' l .. l3 ··rn l .. _ :.rnd C = ··()l O''. what arc the value~ 0 1· the folk•\.\ m~
tatcr.i.t nt:-

"' & B or I JJ & C ,


11 , •.\ rnr :
.ii 1 .-\ sla :
, J .; ··: 11I 1n--
& not B
-.. \\ me a \'IiDL process that 1s equivalent to thl! fo llowing concurrent statemen'. :
\ · B 1 when ( · 1 else 132 \\ hen C - 2 else B3 when C=3 else') :
Drnv, ,-. a, erorm J 1agram to explain ··wan fo r Ons··.
1 xpi au1h()\', hlod , .')tJtcment can he useJ to remo ve dri,er for any signal.

HJ , (3+2=5)
.; DD t1Jp-1lop 1:> ~1milar w a L) nip-flo p. except that the flip-flop can change state
f_l D1 on both the nsing edge and fall ing edge of the clock input. The flip-fl op has
Jircc 1 re~c l input. R. ,md P ·()' resets the flip -fiop to Q .: ' O' independent of the
,uc.t-: 'l!milarl~ . 11 has a direct ) Cl input. S. that sets the flip -Cop to · i rnd-:p(.'nde n: cf
the clock. ,~·rite a VHDL description of a DD flip-flop .
in tht 1ollowing \' HDI. code. A. B. C & D are bit signals that are O at t1me 4ns. lf A
..:hange~ to l at nme 5ns. make a table showing the values of A. B. C & D as a
'. unction of time until time = 18ns (Include IJ. delta). indicate the times at which each
;Jrocess begms executing.
Pl : process ( A)
begin
8 '= l>. after 5 ns :
- <- P, i\fter 2 'I ~ ·
e nd process ;
P Z: prOCllSS
beg in
w:n t on R:
¢ ' '10t t);
J •·= n0t A xor B·
end pro ce ~!- ;

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