DAC

DAC2900
290
0

www.ti.com SBAS166C – JUNE 2001 – REVISED SEPTEMBER 2008

Dual, 10-Bit, 125MSPS

DIGITAL-TO-ANALOG CONVERTER

FEATURES APPLICATIONS
● 125MSPS UPDATE RATE ● COMMUNICATIONS:
● SINGLE SUPPLY: +3.3V or +5V Base Stations, WLL, WLAN
Baseband I/Q Modulation
● HIGH SFDR: 68dB at fOUT = 20MHz
● MEDICAL/TEST INSTRUMENTATION
● LOW GLITCH: 2pV-s
● LOW POWER: 310mW at +5V ● ARBITRARY WAVEFORM GENERATORS (ARB)
● INTERNAL REFERENCE ● DIRECT DIGITAL SYNTHESIS (DDS)
● POWER-DOWN MODE: 23mW

The DAC2900 combines high dynamic performance with

DESCRIPTION a high throughput rate to create a cost-effective solution
The DAC2900 is a monolithic, 10-bit, dual-channel, for a wide variety of waveform-synthesis applications:
high-speed Digital-to-Analog Converter (DAC), and is • Pin compatibility between family members provides
optimized to provide high dynamic performance while 10-bit (DAC2900), 12-bit (DAC2902), and 14-bit
dissipating only 310mW on a +5V single supply. (DAC2904) resolution.
Operating with high update rates of up to 125MSPS, the • Pin compatible to the AD9763 dual DAC.
DAC2900 offers exceptional dynamic performance, and
• Gain matching is typically 0.5% of full-scale, and offset
enables the generation of very high output frequencies
matching is specified at 0.02% max.
suitable for Direct IF applications. The DAC2900 has
been optimized for communications applications in which • The DAC2900 utilizes an advanced CMOS process; the
separate I and Q data are processed while maintaining segmented architecture minimizes output glitch energy,
tight gain and offset matching. and maximizes dynamic performance.
Each DAC has a high-impedance differential-current • All digital inputs are +3.3V and +5V logic compatible.
output, suitable for single-ended or differential analog The DAC2900 has an internal reference circuit, and
output configurations. allows use of an external reference.
• The DAC2900 is available in a TQFP-48 package, and
is specified over the extended industrial temperature
range of –40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2001-2008, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
+VA to AGND ........................................................................ –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V DISCHARGE SENSITIVITY
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD ............................................................................... –6V to +6V
This integrated circuit can be damaged by ESD. Texas Instruments
CLK, PD to DGND ..................................................... –0.3V to VD + 0.3V recommends that all integrated circuits be handled with appropriate
D0-D9 to DGND ......................................................... –0.3V to VD + 0.3V precautions. Failure to observe proper handling and installation pro-
IOUT, IOUT to AGND ........................................................ –1V to VA + 0.3V cedures can cause damage.
BW, BYP to AGND ..................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND ................................................. –0.3V to VA + 0.3V ESD damage can range from subtle performance degradation to
INT/EXT to AGND ...................................................... –0.3V to VA + 0.3V complete device failure. Precision integrated circuits may be more
Junction Temperature .................................................................... +150°C susceptible to damage because very small parametric changes could
Case Temperature ......................................................................... +100°C
cause the device not to meet its published specifications.
Storage Temperature .................................................................... +125°C

PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
DAC2900Y TQFP-48 PFB –40°C to +85°C DAC2900Y DAC2900Y/250 Tape and Reel, 250
" " " " " DAC2900Y/1K Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

PRODUCT EVM ORDERING NUMBER COMMENT

DAC2900 DAC2900-EVM Fully populated evaluation board. See user manual for details.

ELECTRICAL CHARACTERISTICS
At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.

DAC2900Y
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION 10 Bits
Output Update Rate (fCLOCK) 125 MSPS
STATIC ACCURACY(1)
Differential Nonlinearity (DNL) TA = +25°C ±0.25 LSB
TMIN to TMAX –1.0 +1.0 LSB
Integral Nonlinearity (INL) TA = +25°C ±0.25 LSB
TMIN to TMAX –1.0 +1.0 LSB
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR) To Nyquist
fOUT = 1MHz, fCLOCK = 50MSPS 0dBFS Output 70 80 dBc
–6dBFS Output 75 dBc
–12dBFS Output 70 dBc
fOUT = 1MHz, fCLOCK = 26MSPS 80 dBc
fOUT = 2.18MHz, fCLOCK = 52MSPS 80 dBc
fOUT = 5.24MHz, fCLOCK = 52MSPS 80 dBc
fOUT = 10.4MHz, fCLOCK = 78MSPS 75 dBc
fOUT = 15.7MHz, fCLOCK = 78MSPS 71 dBc
fOUT = 5.04MHz, fCLOCK = 100MSPS 80 dBc
fOUT = 20.2MHz, fCLOCK = 100MSPS 68 dBc
fOUT = 20.1MHz, fCLOCK = 125MSPS 61 dBc
fOUT = 40.2MHz, fCLOCK = 125MSPS 56 dBc
Spurious-Free Dynamic Range within a Window
fOUT = 1.0MHz, fCLOCK = 50MSPS 2MHz Span 86 dBc
fOUT = 5.02MHz, fCLOCK = 50MSPS 10MHz Span 80 dBc
fOUT = 5.03MHz, fCLOCK = 78MSPS 10MHz Span 80 dBc
fOUT = 5.04MHz, fCLOCK = 125MSPS 10MHz Span 80 dBc
Total Harmonic Distortion (THD)
fOUT = 1MHz, fCLOCK = 50MSPS –77 –68 dBc
fOUT = 5.02MHz, fCLOCK = 50MSPS –74 dBc
fOUT = 5.03MHz, fCLOCK = 78MSPS –73 dBc
fOUT = 5.04MHz, fCLOCK = 125MSPS –70 dBc
Multitone Power Ratio 8 Tone with 110kHz Spacing
fOUT = 2.0MHz to 2.99MHz, fCLOCK = 65MSPS 0dBFS Output 80 dBc

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ELECTRICAL CHARACTERISTICS (continued)
At TMIN to TMAX, +VA = +5V, +VD = +3.3V, differential transformer coupled output, and 50Ω doubly-terminated, unless otherwise noted. Independent Gain mode.

DAC2900Y
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DYNAMIC PERFORMANCE (Cont.)
Signal-to-Noise Ratio (SNR) 0dBFS Output 62 dBc
fOUT = 5.02MHz, fCLOCK = 50MHz
Signal-to-Noise and Distortion (SINAD) 0dBFS Output 61.5 dBc
fOUT = 5.02MHz, fCLOCK = 50MHz
Channel Isolation
fOUT = 1MHz, fCLOCK = 52MSPS 85 dBc
fOUT = 20MHz, fCLOCK = 125MSPS 77 dBc
Output Settling Time(2) to 0.1% 30 ns
Output Rise Time(2) 10% to 90% 2 ns
Output Fall Time(2) 10% to 90% 2 ns
Glitch Impulse 2 pV-s
DC ACCURACY
Full-Scale Output Range(3)(FSR) All Bits HIGH, IOUT 2 20 mA
Output Compliance Range –1.0 +1.25 V
Gain Error—Full-Scale With Internal Reference –5 ±1 +5 %FSR
Gain Error With External Reference –2.5 ±1 +2.5 %FSR
Gain Matching With Internal Reference –2.0 0.5 +2.0 %FSR
Gain Drift With Internal Reference ±50 ppmFSR/°C
Offset Error With Internal Reference –0.02 +0.02 %FSR
Offset Drift With Internal Reference ±0.2 ppmFSR/°C
Power-Supply Rejection, +VA +5V, ±10% –0.2 +0.2 %FSR/V
Power-Supply Rejection, +VD +3.3V, ±10% –0.025 +0.025 %FSR/V
Output Noise IOUT = 20mA, RLOAD = 50Ω 50 pA/√Hz
IOUT = 2mA 30 pA/√Hz
Output Resistance 200 kΩ
Output Capacitance IOUT, IOUT to Ground 6 pF
REFERENCE/CONTROL AMP
Reference Voltage +1.18 +1.25 +1.31 V
Reference Voltage Drift ±50 ppmFSR/°C
Reference Output Current 100 nA
Reference Multiplying Bandwidth 0.3 MHz
Input Compliance Range +0.5 +1.25 V
DIGITAL INPUTS
Logic Coding Straight Binary
Logic High Voltage, VIH +VD = +5V 3.5 5 V
Logic Low Voltage, VIL +VD = +5V 0 1.2 V
Logic High Voltage, VIH +VD = 3.3V 2 3 V
Logic Low Voltage, VIL +VD = 3.3V 0 0.8 V
Logic High Current, IIH(4) +VD = 3.3V ±10 µA
Logic Low Current +VD = 3.3V ±10 µA
Input Capacitance 5 pF
POWER SUPPLY
Supply Voltages
+VA +3.0 +5 +5.5 V
+VD +3.0 +3.3 +5.5 V
Supply Current
IVA(5) VA = +5V, lOUT = 20mA 58 65 mA
IVA(5) Power-Down Mode 1.7 3 mA
IVD(5) 4.2 7 mA
IVD(6) 17 19.5 mA
Power Dissipation(5) VA = +5V, VD = 3.3V, lOUT = 20mA 310 350 mW
Power Dissipation(6) VA = +5V, VD = 3.3V, lOUT = 20mA 348 390 mW
Power Dissipation(5) VA = +5V, VD = 3.3V, lOUT = 2mA 130 mW
Power Dissipation Power-Down Mode 23 38 mW
Thermal Resistance, TQFP-48
θJA 60 °C/W
θJC 13 °C/W
TEMPERATURE RANGE
Specified Ambient –40 +85 °C
Operating Ambient –40 +85 °C

NOTES: (1) At output lOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω load. (3) Nominal full-scale output current is 32 x IREF; see Application
Information section for details. (4) Typically 45µA for the PD pin, which has an internal pull-down resistor. (5) Measured at fCLOCK = 25MSPS and fOUT = 1MHz.
(6) Measured at fCLOCK = 100MSPS and fOUT = 40MHz.

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PIN CONFIGURATION
Top View TQFP-48

AGND
GSET
REFIN
FSA1

FSA2
IOUT1

IOUT1

IOUT2

IOUT2
+VA
NC

PD
48 47 46 45 44 43 42 41 40 39 38 37

D9_1 (MSB) 1 36 NC

D8_1 2 35 NC

D7_1 3 34 NC

D6_1 4 33 NC

D5_1 5 32 D0_2

D4_1 6 31 D1_2
DAC2900
D3_1 7 30 D2_2

D2_1 8 29 D3_2

D1_1 9 28 D4_2

D0_1 10 27 D5_2

NC 11 26 D6_2

NC 12 25 D7_2

13 14 15 16 17 18 19 20 21 22 23 24
NC

NC

DGND

+VD

WRT1

CLK1

CLK2

WRT2

DGND

+VD

D9_2 (MSB)

D8_2

PIN DESCRIPTIONS
PIN DESIGNATOR DESCRIPTION
1-10 D[9:0]_1 Data Port DAC1, Data Bit 9 (MSB) to Bit 0 (LSB).
11-14 NC No Connection
15 DGND Digital Ground
16 +VD Digital Supply, +3.0V to +5.5V
17 WRT1 DAC1 Input Latches Write Signal
18 CLK1 Clock Input DAC1
19 CLK2 Clock Input DAC2
20 WRT2 DAC2 Input Latches Write Signal
21 DGND Digital Ground
22 +VD Digital Supply, +3.0V to +5.5V
23-32 D[9:0]_2 Data Port DAC2, Data Bit 9 (MSB) to Bit 0 (LSB).
33-36 NC No Connection
37 PD Power-Down Function Control Input; H = DAC in power-down mode; L = DAC in normal operation (Internal pull-down for default L).
38 AGND Analog Ground
39 IOUT2 Current Output DAC2. Full-scale with all bits of data port 2 high.
40 IOUT2 Complementary Current Output DAC2. Full-scale with all bits of data port 2 low.
41 FSA2 Full-Scale Adjust, DAC2. Connect External RSET Resistor
42 GSET Gain-Setting Mode (H = 1 Resistor, L = 2 Resistor)
43 REFIN Internal Reference Voltage output; External Reference Voltage input. Bypass with 0.1µF to AGND for internal reference
operation.
44 FSA1 Full-Scale Adjust, DAC1. Connect External RSET Resistor
45 IOUT1 Complementary Current Output DAC1. Full-scale with all bits of data port 1 low.
46 IOUT1 Current Output DAC1. Full-scale with all bits of data port 1 high.
47 +VA Analog Supply, +3.0V to +5.5V
48 NC No Connection

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TIMING DIAGRAM

tS tH

DATA IN D[9:0](n) D[9:0](n + 1)

tLPW

WRT1
WRT2
tCPW

CLK1
CLK2
tCW tSET

IOUT1
IOUT(n)
50% IOUT(n + 1)
IOUT2

tPD

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tS Input Setup Time 2 ns

tH Input Hold Time 1.5 ns
tLPW, tCPW Latch/Clock Pulsewidth 3.5 4 ns
tCW Delay Rising CLK Edge to 0 tPW – 2 ns
Rising WRT Edge
tPD Propagation Delay 1 ns
tSET Settling Time (0.1%) 30 ns

DIGITAL INPUTS AND TIMING The two converter channels within the DAC2900 consist of
The data input ports of the DAC2900 accept a standard two independent, 10-bit, parallel data ports. Each DAC
positive coding with data bit D9 being the most significant channel is controlled by its own set of write (WRT1, WRT2)
bit (MSB). The converter outputs support a clock rate of up and clock (CLK1, CLK2) inputs. Here, the WRT lines
to 125MSPS. The best performance will typically be achieved control the channel input latches and the CLK lines control
with a symmetrical duty cycle for write and clock; however, the DAC latches. The data is first loaded into the input latch
the duty cycle may vary as long as the timing specifications by a rising edge of the WRT line. This data is presented to
are met. Also, the setup and hold times may be chosen the DAC latch on the following falling edge of the WRT
within their specified limits. signal. On the next rising edge of the CLK line, the DAC is
updated with the new data and the analog output signal will
All digital inputs of the DAC2900 are CMOS-compatible. change accordingly. The double latch architecture of the
The logic thresholds depend on the applied digital supply DAC2900 results in a defined sequence for the WRT and
voltages, such that they are set to approximately half the CLK signals, expressed by parameter tCW. A correct timing
supply voltage: Vth = +VD/2 (±20% tolerance). The DAC2900 is observed when the rising edge of CLK occurs at the same
is designed to operate with a digital supply (+VD) of +3.0V time, or before, the rising edge of the WRT signal. This
to +5.5V. condition can simply be met by connecting the WRT and
CLK lines together. Note that all specifications were mea-
sured with the WRT and CLK lines connected together.

DAC2900 5
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TYPICAL CHARACTERISTICS
At TA = +25°C, +VA = +5V, +VD = +3.3V, differential output IOUTFS = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise noted.

TYPICAL DNL TYPICAL INL

0.50 0.50
0.40 0.40
0.30 0.30
0.20 0.20
DNL (LSBs)

INL (LSBs)
0.10 0.10
0.00 0.00
–0.10 –0.10
–0.20 –0.20
–0.30 –0.30
–0.40 –0.40
–0.50 –0.50
0 200 400 600 800 1k 0 200 400 600 800 1k
Code Code

SFDR vs fOUT AT 26MSPS SFDR vs fOUT AT 52MSPS

85 85
0dBFS 0dBFS

80 80
SFDR (dBc)

SFDR (dBc)

75 75
–6dBFS –6dBFS

70 70
–12dBFS –12dBFS

65 65

60 60
0 2 4 6 8 10 12 0 5 10 15 20 25
fOUT (MHz) fOUT (MHz)

SFDR vs fOUT AT 78MSPS SFDR vs fOUT AT 100MSPS

85 85
0dBFS 0dBFS
80 80
–6dBFS
–6dBFS 75
75
SFDR (dBc)

SFDR (dBc)

70
70 –12dBFS
–12dBFS 65
65
60

60 55

55 50
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 40 45
fOUT (MHz) fOUT (MHz)

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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VA = +5V, +VD = +3.3V, differential output IOUTFS = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise noted.

SFDR vs fOUT AT 125MSPS SFDR vs IOUT AND fOUT AT 78MSPS, 0dBFS

85 84
82
80 80
–6dBFS 5mA 20mA
78
75
–12dBFS 76
SFDR (dBc)

SFDR (dBc)
70 74
10mA
72
65 70
0dBFS 2mA
68
60
66
55 64
62
50 60
0 10 20 30 40 50 60 0 5 10 15 20 25
fOUT (MHz) fOUT (MHz)

SFDR vs TEMPERATURE AT 125MSPS, 0dBFS GAIN AND OFFSET DRIFT

90 0.8 0.004

85 0.6 0.003
2MHz
0.4 Offset Error 0.002
80

Offset Error (% FS)

Gain Error (% FS)

10MHz
SFDR (dBc)

75 0.2 0.001

70 0 0
20MHz
65 –0.2 –0.001
Gain Error
60 40MHz –0.4 –0.002

55 –0.6 –0.003

50 –0.8 –0.004
–40 –20 0 20 40 60 80 85 –40 –20 0 20 40 60 80 85
Temperature (°C) Temperature (°C)

IVD vs RATIO AT +VD = 3.3V IVA vs IOUTFS

25 60
125MSPS 55
20 100MSPS 50
45
78MSPS
15 40
IVD (mA)

IVA (mA)

52MSPS 35
10 30

26MSPS 25
5 20
15
0 10
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0 5 10 15 20 25
Ratio (fOUT/fCLK) IOUTFS (mA)

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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, +VA = +5V, +VD = +3.3V, differential output IOUTFS = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise noted.

SINGLE-TONE SFDR SINGLE-TONE SFDR

10 10
fCLOCK = 52MSPS fCLOCK = 100MSPS
0 0
fOUT = 5.23MHz fOUT = 20.2MHz
–10 –10
Amplitude = 0dBFS Amplitude = 0dBFS
Magnitude (dBm)

Magnitude (dBm)
–20 –20
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
0 4 8 12 16 20 0 10 20 30 40 50
Frequency (MHz) Frequency (MHz)

DUAL-TONE SFDR FOUR-TONE SFDR

10 10
fCLOCK = 78MSPS fCLOCK = 50MSPS
0 0
fOUT1 = 9.44MHz fOUT1 = 6.25MHz
–10 –10
fOUT2 = 10.44MHz fOUT2 = 6.75MHz
Magnitude (dBm)

Magnitude (dBm)

–20 Amplitude = 0dBFS –20 fOUT3 = 7.25MHz

–30 –30 fOUT4 = 7.75MHz
–40 –40 Amplitude = 0dBFS
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
0 7.8 15.6 23.4 31.2 39.0 0 5 10 15 20 25
Frequency (MHz) Frequency (MHz)

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APPLICATION INFORMATION DAC TRANSFER FUNCTION
The full-scale output current, IOUTFS, is the summation of the
THEORY OF OPERATION
two complementary output currents:
The architecture of the DAC2900 uses the current steering
technique to enable fast switching and a high update rate.
IOUTFS = IOUT + IOUT (1)
The core element within the monolithic DAC is an array of
segmented current sources that are designed to deliver a full-
scale output current of up to 20mA, as shown in Figure 1. An The individual output currents depend on the DAC code and
internal decoder addresses the differential current switches can be expressed as:
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output IOUT = IOUTFS × (Code/1024) (2)
summing node, IOUT or IOUT. The complementary outputs
deliver a differential output signal, which improves the
IOUT = IOUTFS × (1023 – Code)/1024 (3)
dynamic performance through reduction of even-order har-
monics, common-mode signals (noise), and double the peak-
where Code is the decimal representation of the DAC data
to-peak output signal swing by a factor of two, compared to
input word. Additionally, IOUTFS is a function of the refer-
single-ended operation.
ence current IREF, which is determined by the reference
The segmented architecture results in a significant reduction voltage and the external setting resistor, RSET.
of the glitch energy, improves the dynamic performance
(SFDR), and DNL. The current outputs maintain a very high
IOUTFS = 32 × IREF = 32 × VREF /RSET (4)
output impedance of greater than 200kΩ.
The full-scale output current is determined by the ratio of the
In most cases the complementary outputs will drive resistive
internal reference voltage (1.24V) and an external resistor,
loads or a terminated transformer. A signal voltage will
RSET. The resulting IREF is internally multiplied by a factor
develop at each output according to:
of 32 to produce an effective DAC output current that can
range from 2mA to 20mA, depending on the value of RSET.
VOUT = IOUT × RLOAD (5)
The DAC2900 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the VOUT = IOUT × RLOAD (6)
decoder logic, while the analog section consists of the
current source array with its associated switches, and the
reference circuitry.

+VD +VD +VA

lOUT1
Data Input Input DAC DAC1
Port 1 Latch 1 Latch 1 Segmented Switches
D[9:0]_1 Current Sources lOUT1

WRT1 REFIN
FSA1
CLK1 Reference
FSA2
DAC2900 Control Amplifier
CLK2 GSET
PD
WRT2

lOUT2
Data Input Input DAC DAC2
Port 2 Latch 2 Latch 2 Segmented Switches
D[9:0]_2 Current Sources lOUT2

DGND DGND AGND

FIGURE 1. Block Diagram of the DAC2900.

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The value of the load resistance is limited by the output be adapted to the output of the DAC2900 by selecting a
compliance specification of the DAC2900. To maintain suitable transformer while maintaining optimum voltage
specified linearity performance, the voltage for IOUT and levels at IOUT and IOUT. Furthermore, using the differential
IOUT should not exceed the maximum allowable compliance output configuration in combination with a transformer will
range. be instrumental for achieving excellent distortion perfor-
The two single-ended output voltages can be combined to mance. Common-mode errors, such as even-order harmon-
find the total differential output swing: ics or noise, can be substantially reduced. This is particularly
the case with high output frequencies.
For those applications requiring the optimum distortion and
(2 × Code – 1023)
VOUTDIFF = VOUT – VOUT = × IOUTFS × RLOAD (7) noise performance, it is recommended to select a full-scale
1024
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
ANALOG OUTPUTS consumption, but can tolerate a slightly reduced perfor-
The DAC2900 provides two complementary current out- mance level.
puts, IOUT and IOUT. The simplified circuit of the analog
output stage representing the differential topology is shown OUTPUT CONFIGURATIONS
in Figure 2. The output impedance of IOUT and IOUT results
The current outputs of the DAC2900 allow for a variety of
from the parallel combination of the differential switches,
configurations, some of which are illustrated in Table I. As
along with the current sources and associated parasitic
mentioned previously, utilizing the converter's differential
capacitances.
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
or a differential amplifier configuration. The transformer
configuration is ideal for most applications with ac coupling,
+VA while op amps will be suitable for a DC-coupled configura-
DAC2900
tion.

INPUT CODE (D9 - D0) IOUT IOUT

11 1111 1111 20mA 0mA
00 0000 0000 10mA 10mA
00 0000 0000 0mA 20mA

TABLE I. Input Coding versus Analog Output Current.

IOUT IOUT
The single-ended configuration may be considered for appli-
RL RL cations requiring a unipolar output voltage. Connecting a
resistor from either one of the outputs to ground will convert
the output current into a ground-referenced voltage signal.
To improve on the DC linearity an I-to-V converter can be
used instead. This will result in a negative signal excursion
FIGURE 2. Equivalent Analog Output.
and, therefore, requires a dual supply amplifier.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive DIFFERENTIAL WITH TRANSFORMER
compliance. The negative limit of –1V is given by the Using an RF transformer provides a convenient way of convert-
breakdown voltage of the CMOS process, and exceeding it ing the differential output signal into a single-ended signal
will compromise the reliability of the DAC2900, or even while achieving excellent dynamic performance (see Figure 3).
cause permanent damage. With the full-scale output set to The appropriate transformer should be carefully selected based
20mA, the positive compliance equals 1.25V, operating with on the output frequency spectrum and impedance requirements.
an analog supply of +VA = 5V. Note that the compliance The differential transformer configuration has the benefit of
range decreases to about 1V for a selected output current of significantly reducing common-mode signals, thus improving
IOUTFS = 2mA. Care should be taken that the configuration the dynamic performance over a wide range of frequencies.
of the DAC2900 does not exceed the compliance range to Furthermore, by selecting a suitable impedance ratio (winding
avoid degradation of the distortion performance and integral ratio), the transformer can be used to provide optimum imped-
linearity. ance matching while controlling the compliance voltage for the
Best distortion performance is typically achieved with the converter outputs. The model shown, ADTT1-1 (by Mini-
maximum full-scale output signal limited to approximately Circuits), has a 1:1 ratio and may be used to interface the
0.5VPP. This is the case for a 50Ω doubly terminated load DAC2900 to a 50Ω load. This results in a 25Ω load for each of
and a 20mA full-scale output current. A variety of loads can the outputs, IOUT and IOUT. The output signals are AC coupled
and inherently isolated because of its magnetic coupling.

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As shown in Figure 3, the transformer center tap is con- The OPA680 is configured for a gain of two. Therefore,
nected to ground. This forces the voltage swing on IOUT and operating the DAC2900 with a 20mA full-scale output will
IOUT to be centered at 0V. In this case the two resistors, RL, produce a voltage output of ±1V. This requires the amplifier
may be replaced with one, RDIFF, or omitted altogether. This to operate from a dual power supply ( 5V). The tolerance of
approach should only be used if all components are close to the resistors typically sets the limit for the achievable com-
each other, and if the VSWR is not important. A complete mon-mode rejection. An improvement can be obtained by
power transfer from the DAC output to the load can be fine tuning resistor R4.
realized, but the output compliance range should be ob- This configuration typically delivers a lower level of AC
served. Alternatively, if the center tap is not connected, the performance than the previously discussed transformer solu-
signal swing will be centered at RL × IOUTFS/2. However, in tion because the amplifier introduces another source of
this case, the two resistors, RL, must be used to enable the distortion. Suitable amplifiers should be selected based on
necessary DC-current flow for both outputs. their slew-rate, harmonic distortion, and output swing capa-
bilities. High-speed amplifiers like the OPA680 or OPA687
ADTT1-1
may be considered. The AC performance of this circuit may
(Mini-Circuits) be improved by adding a small capacitor, CDIFF, between the
1:1 outputs IOUT and IOUT (as shown in Figure 4). This will
IOUT
RL introduce a real pole to create a low-pass filter in order to
Optional 50Ω slew-limit the DAC fast output signal steps, which otherwise
DAC2900 RS
RDIFF
could drive the amplifier into slew-limitations or into an
IOUT overload condition; both would cause excessive distortion.
RL The difference amplifier can easily be modified to add a
50Ω level shift for applications requiring the single-ended output
voltage to be unipolar (that is, swing between 0V and +2V).

FIGURE 3. Differential Output Configuration Using an RF DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION

Transformer.
The circuit example of Figure 5 shows the signal output
currents connected into the summing junctions of the dual
DIFFERENTIAL CONFIGURATION USING AN OP AMP
voltage-feedback op amp OPA2680 that is set up as a
If the application requires a DC-coupled output, a difference transimpedance stage, or I-to-V converter. With this circuit,
amplifier may be considered, as shown in Figure 4. Four the DAC output will be kept at a virtual ground, minimizing
external resistors are needed to configure the voltage-feed- the effects of output impedance variations, which results in
back op amp OPA680 as a difference amplifier performing the best DC linearity (INL). As mentioned previously, care
the differential to single-ended conversion. Under the shown should be taken not to drive the amplifier into slew-rate
configuration, the DAC2900 generates a differential output limitations, and produce unwanted distortion.
signal of 0.5VPP at the load resistors, RL. The resistor values
shown were selected to result in a symmetric 25Ω loading
for each of the current outputs since the input impedance of +5V
50Ω
the difference amplifier is in parallel to resistors RL, and
should be considered. 1/2
–VOUT = IOUT • RF1
OPA2680

R2 DAC2900 RF1
402Ω

R1 CF1
IOUT CD1
200Ω
IOUT
DAC2900 OPA680 VOUT RF2
IOUT
COPT R3 CF2
200Ω IOUT CD2
–5V +5V

RL RL R4
26.1Ω 28.7Ω 402Ω 1/2
OPA2680 –VOUT = IOUT • RF2

50Ω
FIGURE 4. Difference Amplifier Provides Differential to –5V
Single-Ended Conversion and DC-Coupling.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.

DAC2900 11
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The DC gain for this circuit is equal to feedback resistor RF. INTERNAL REFERENCE OPERATION
At high frequencies, the DAC output impedance (CD1, CD2) The DAC2900 has an on-chip reference circuit, which con-
will produce a zero in the noise gain for the OPA2680 that sists of a 1.24V bandgap reference and two control amplifi-
may cause peaking in the closed-loop frequency response. ers, one for each DAC. The full-scale output current (IOUTFS)
CF is added across RF to compensate for this noise gain of the DAC2900 is determined by the reference voltage,
peaking. To achieve a flat transimpedance frequency re- VREF, and the value of resistor RSET. IOUTFS can be calcu-
sponse, the pole in each feedback network should be set to: lated by:
IOUTFS = 32 × IREF = 32 × VREF / RSET (10)
1 GBP
= (8)
2 πR F C F 4 πR F C D As shown in Figure 7, the external resistor RSET connects to
the FSA pin (Full-Scale Adjust). The reference control
with GBP = Gain Bandwidth Product of OPA
amplifier operates as a V-to-I converter producing a refer-
ence current, IREF, which is determined by the ratio of VREF
which will give a corner frequency f-3dB of approximately: and RSET (see Equation 10). The full-scale output current,
IOUTFS, results from multiplying IREF by a fixed factor of 32.

GBP
f –3dB = (9)
2 πR F C D +5V

The full-scale output voltage is simply defined by the prod-

uct of IOUTFS × RF, and has a negative unipolar excursion. To DAC2900 +VA

improve on the ac performance of this circuit, adjustment of VREF

IREF =
RF and/or IOUTFS should be considered. Further extensions of RSET
FSA
this application example may include adding a differential Ref Current
filter at the OPA2680 output followed by a transformer, in REFIN
Control Sources
Amp
order to convert to a single-ended signal. RSET
2kΩ
0.1µF
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC +1.24V Ref.
outputs, a simple current-to-voltage conversion can be ac-
complished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of FIGURE 7. Internal Reference Configuration.
0V to 0.5V into the 25Ω load.
Using the internal reference, a 2kΩ resistor value results in
a full-scale output of approximately 20mA. Resistors with a
tolerance of 1% or better should be considered. Selecting
IOUTFS = 20mA
VOUT = 0V to +0.5V higher values, the output current can be adjusted from 20mA
IOUT down to 2mA. Operating the DAC2900 at lower than 20mA
DAC2900 output currents may be desirable for reasons of reducing the
IOUT 50Ω 50Ω
total power consumption, improving the distortion perfor-
25Ω mance, or observing the output compliance voltage limita-
tions for a given load condition.
It is recommended to bypass the REFIN pin with a ceramic
chip capacitor of 0.1µF or more. The control amplifier is
FIGURE 6. Driving a Doubly Terminated 50Ω Cable Directly. internally compensated, and its small signal bandwidth is
approximately 0.3MHz.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor, may be mutu-
ally adjusted to provide the desired output signal swing and
performance.

12 DAC2900
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GAIN SETTING OPTIONS EXTERNAL REFERENCE OPERATION
The full-scale output current on the DAC2900 can be set two The internal reference can be disabled by simply applying an
ways: either for each of the two DAC channels independently external reference voltage into the REFIN pin, which in this
or for both channels simultaneously. For the independent gain case functions as an input, as shown in Figure 8. The use of
set mode, the GSET pin (pin 42) must be LOW (that is, an external reference may be considered for applications that
connected to AGND). In this mode, two external resistors are require higher accuracy and drift performance, or to add the
required—one RSET connected to the FSA1 pin (pin 44) and ability of dynamic gain control.
the other to the FSA2 pin (pin 41). In this configuration, the While a 0.1µF capacitor is recommended to be used with the
user has the flexibility to set and adjust the full-scale output internal reference, it is optional for the external reference
current for each DAC independently, allowing for the com- operation. The reference input, REFIN, has a high input
pensation of possible gain mismatches elsewhere within the impedance (1MΩ) and can easily be driven by various
transmit signal path. sources. Note that the voltage range of the external reference
Alternatively, bringing the GSET pin HIGH (that is, con- should stay within the compliance range of the reference
nected to +VA), the DAC2900 will switch into the simulta- input (0.1V to 1.25V).
neous gain set mode. Now the full-scale output current of both
DAC channels is determined by only one external RSET POWER-DOWN MODE
resistor connected to the FSA1 pin, while any present resistor
at the FSA2 pin must be removed. The formula for deriving The DAC2900 features a power-down function which can
the correct RSET remains unchanged (for example, RSET = 2kΩ be used to reduce the total supply current to less than 6mA
will result in a 20mA output for both DACs). over the specified supply range of 3.0V to 5.5V. Applying
a logic HIGH to the PD pin will initiate the power-down
mode, while a logic LOW enables normal operation. When
left unconnected, an internal active pull-down circuit will
enable the normal operation of the converter.

+5V

DAC2900 +VA

VREF
IREF =
RSET
FSA
Ref Current
Control Sources
External REFIN Amp
Reference

RSET

+1.24V Ref.

FIGURE 8. External Reference Configuration.

DAC2900 13
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GROUNDING, DECOUPLING AND Low noise is required for all supply and ground connections
LAYOUT INFORMATION to the DAC2900. It is recommended to use a multilayer PCB
Proper grounding and bypassing, short lead length, and the use utilizing separate power and ground planes. Mixed signal
of ground planes are particularly important for high-frequency designs require particular attention to the routing of the
designs. Multilayer PCBs are recommended for best perfor- different supply currents and signal traces. Generally, analog
mance since they offer distinct advantages such as minimiza- supply and ground planes should only extend into analog
tion of ground impedance, separation of signal layers by signal areas, such as the DAC output signal and the refer-
ground layers, etc. ence signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
The DAC2900 uses separate pins for its analog and digital
digital input lines connecting to the converter, as well as the
supply and ground connections. The placement of the decou-
clock signal. The analog and digital ground planes should be
pling capacitor should be such that the analog supply (+VA)
joined together at one point underneath the DAC. This can
is bypassed to the analog ground (AGND), and the digital
be realized with a short track of approximately 1/8 inch
supply bypassed to the digital ground (DGND). In most
(3mm).
cases 0.1µF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep The power to the DAC2900 should be provided through the
in mind that their effectiveness largely depends on the use of wide pcb runs or planes. Wide runs will present a
proximity to the individual supply and ground pins. There- lower trace impedance, further optimizing the supply decou-
fore they should be located as close as physically possible to pling. The analog and digital supplies for the converter
those device leads. Whenever possible, the capacitors should should only be connected together at the supply connector of
be located immediately under each pair of supply/ground the pc board. In the case of only one supply voltage being
pins on the reverse side of the pc board. This layout ap- available to power the DAC, ferrite beads along with bypass
proach will minimize the parasitic inductance of component capacitors may be used to create an LC filter. This will
leads and PCB runs. generate a low-noise analog supply voltage, which can then
be connected to the +VA supply pin of the DAC2900.
Further supply decoupling with surface-mount tantalum ca-
pacitors (1µF to 4.7µF) may be added as needed in proxim- While designing the layout, it is important to keep the analog
ity of the converter. signal traces separated from any digital line, in order to
prevent noise coupling onto the analog signal path.

14 DAC2900
SBAS166C
www.ti.com
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

1 – Updated front page to standard format.
9/08 C 2 Pkg/Ordering Info Table Updated Package/Ordering Information table.
3 Electrical Characteristics Changed values for Supply Current and Power Dissipation.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DAC2900 15
SBAS166C
www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

DAC2900Y/1K ACTIVE TQFP PFB 48 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2900Y
& no Sb/Br)
DAC2900Y/250 ACTIVE TQFP PFB 48 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 DAC2900Y
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC2900Y/1K TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
DAC2900Y/250 TQFP PFB 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC2900Y/1K TQFP PFB 48 1000 367.0 367.0 38.0
DAC2900Y/250 TQFP PFB 48 250 367.0 367.0 38.0

Pack Materials-Page 2
 MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

0,27
0,50 0,08 M
0,17

36 25

37 24

48 13

0,13 NOM
1 12

5,50 TYP
7,20
SQ Gage Plane
6,80
9,20
SQ
8,80 0,25
0,05 MIN 0°– 7°
1,05
0,95
0,75
Seating Plane 0,45

0,08
1,20 MAX

4073176 / B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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